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authorMatthew Vick <matthew.vick@intel.com>2011-12-23 02:32:51 -0800
committerBen Hutchings <bhutchings@solarflare.com>2012-01-12 16:33:38 +0000
commitf4998a80324b1386b9e687b9059e64b620cf87b0 (patch)
tree98f1a5f5d4dc88349da502beee7f5f1d4e57f3f5
parent2976637383827bb0733267df02c7093f0d6fdde4 (diff)
downloadethtool-f4998a80324b1386b9e687b9059e64b620cf87b0.tar.gz
ethtool: Correct register dump offsets for Intel 82575 chipsets.
When support was added to dump the registers on 82575 chipset devices, six register offsets (receive/transmit desc length, head, and tail) were incorrectly mapped. This patch remaps the offsets to the correct registers. Signed-off-by: Matthew Vick <matthew.vick@intel.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
-rw-r--r--igb.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/igb.c b/igb.c
index ec35d36..e0ccef9 100644
--- a/igb.c
+++ b/igb.c
@@ -200,13 +200,13 @@ igb_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
/* Receive descriptor registers */
fprintf(stdout,
"0x02808: RDLEN (Receive desc length) 0x%08X\n",
- regs_buff[142]);
+ regs_buff[137]);
fprintf(stdout,
"0x02810: RDH (Receive desc head) 0x%08X\n",
- regs_buff[146]);
+ regs_buff[141]);
fprintf(stdout,
"0x02818: RDT (Receive desc tail) 0x%08X\n",
- regs_buff[150]);
+ regs_buff[145]);
/* Transmit control register */
reg = regs_buff[38];
@@ -226,13 +226,13 @@ igb_dump_regs(struct ethtool_drvinfo *info, struct ethtool_regs *regs)
/* Transmit descriptor registers */
fprintf(stdout,
"0x03808: TDLEN (Transmit desc length) 0x%08X\n",
- regs_buff[214]);
+ regs_buff[219]);
fprintf(stdout,
"0x03810: TDH (Transmit desc head) 0x%08X\n",
- regs_buff[218]);
+ regs_buff[223]);
fprintf(stdout,
"0x03818: TDT (Transmit desc tail) 0x%08X\n",
- regs_buff[222]);
+ regs_buff[227]);
fprintf(stdout,