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| author | Dmitry Kasatkin <dmitry.kasatkin@intel.com> | 2012-12-18 14:56:48 +0200 |
|---|---|---|
| committer | Werner Koch <wk@gnupg.org> | 2012-12-18 19:33:04 +0100 |
| commit | efd7002188e6d50013e4d9a920a8b9afa9d210e5 (patch) | |
| tree | 09adb14c6f19c50a45ae5c2fb3067c08435506d5 /src/hwfeatures.c | |
| parent | bfe4dc11bb822cbc5bf2b425e5a5a2867a904518 (diff) | |
| download | libgcrypt-efd7002188e6d50013e4d9a920a8b9afa9d210e5.tar.gz | |
Add support for using DRNG random number generator
* configure.ac: Add option --disable-drng-support.
(ENABLE_DRNG_SUPPORT): New.
* random/rndhw.c (USE_DRNG): New.
(rdrand_long, rdrand_nlong, poll_drng): New.
(_gcry_rndhw_poll_fast, _gcry_rndhw_poll_slow): Call poll function.
* src/g10lib.h (HWF_INTEL_RDRAND): New.
* src/global.c (hwflist): Add "intel-rdrand".
* src/hwfeatures.c (detect_x86_64_gnuc) [ENABLE_DRNG_SUPPORT]: Detect
RDRAND.
(detect_ia32_gnuc) [ENABLE_DRNG_SUPPORT]: Detect RDRAND.
--
This patch provides support for using Digital Random Number Generator (DRNG)
engine, which is available on the latest Intel's CPUs. DRNG engine is
accesible via new the RDRAND instruction.
This patch adds the following:
- support for disabling using of rdrand instruction
- checking for RDRAND instruction support using cpuid
- RDRAND usage implementation
Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@intel.com>
ChangeLog and editorial changes by wk.
Diffstat (limited to 'src/hwfeatures.c')
| -rw-r--r-- | src/hwfeatures.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/hwfeatures.c b/src/hwfeatures.c index 82c435b6..e89c8259 100644 --- a/src/hwfeatures.c +++ b/src/hwfeatures.c @@ -134,6 +134,20 @@ detect_x86_64_gnuc (void) : "%eax", "%ebx", "%ecx", "%edx", "cc" ); #endif /*#ifdef ENABLE_AESNI_SUPPORT*/ +#ifdef ENABLE_DRNG_SUPPORT + asm volatile + ("movl $1, %%eax\n\t" /* Get CPU info and feature flags. */ + "cpuid\n" + "testl $0x40000000, %%ecx\n\t" /* Test bit 30. */ + "jz .Lno_rdrand%=\n\t" /* No RDRAND support. */ + "orl $512, %0\n" /* Set our HWF_INTEL_RDRAND bit. */ + + ".Lno_rdrand%=:\n" + : "+r" (hw_features) + : + : "%eax", "%ebx", "%ecx", "%edx", "cc" + ); +#endif /* #ifdef ENABLE_DRNG_SUPPORT */ } #endif /* __x86_64__ && __GNUC__ */ @@ -267,6 +281,22 @@ detect_ia32_gnuc (void) : "%eax", "%ecx", "%edx", "cc" ); #endif /*ENABLE_AESNI_SUPPORT*/ +#ifdef ENABLE_DRNG_SUPPORT + asm volatile + ("pushl %%ebx\n\t" /* Save GOT register. */ + "movl $1, %%eax\n\t" /* Get CPU info and feature flags. */ + "cpuid\n" + "popl %%ebx\n\t" /* Restore GOT register. */ + "testl $0x40000000, %%ecx\n\t" /* Test bit 30. */ + "jz .Lno_rdrand%=\n\t" /* No RDRAND support. */ + "orl $512, %0\n" /* Set our HWF_INTEL_RDRAND bit. */ + + ".Lno_rdrand%=:\n" + : "+r" (hw_features) + : + : "%eax", "%ecx", "%edx", "cc" + ); +#endif /*ENABLE_DRNG_SUPPORT*/ } #endif /* __i386__ && SIZEOF_UNSIGNED_LONG == 4 && __GNUC__ */ |