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authorAleksey Makarov <aleksey.makarov@caviumnetworks.com>2016-02-11 13:53:08 +0000
committerTejun Heo <tj@kernel.org>2016-02-11 10:12:04 -0500
commita2127e400edd2258fda6d83fe8b10b878a3595d9 (patch)
tree47e1dc70456a5d7231295825a152d98e060d3d81 /Documentation/devicetree/bindings/mips
parent287e6611ab1eac76c2c5ebf6e345e04c80ca9c61 (diff)
downloadlinux-a2127e400edd2258fda6d83fe8b10b878a3595d9.tar.gz
libata: support AHCI on OCTEON platform
The OCTEON SATA controller is currently found on cn71XX devices. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Vinita Gupta <vgupta@caviumnetworks.com> Signed-off-by: Aleksey Makarov <aleksey.makarov@auriga.com> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Tejun Heo <tj@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mips')
-rw-r--r--Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt42
1 files changed, 42 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt b/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt
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+++ b/Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt
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+* UCTL SATA controller glue
+
+UCTL is the bridge unit between the I/O interconnect (an internal bus)
+and the SATA AHCI host controller (UAHC). It performs the following functions:
+ - provides interfaces for the applications to access the UAHC AHCI
+ registers on the CN71XX I/O space.
+ - provides a bridge for UAHC to fetch AHCI command table entries and data
+ buffers from Level 2 Cache.
+ - posts interrupts to the CIU.
+ - contains registers that:
+ - control the behavior of the UAHC
+ - control the clock/reset generation to UAHC
+ - control endian swapping for all UAHC registers and DMA accesses
+
+Properties:
+
+- compatible: "cavium,octeon-7130-sata-uctl"
+
+ Compatibility with the cn7130 SOC.
+
+- reg: The base address of the UCTL register bank.
+
+- #address-cells, #size-cells, ranges and dma-ranges must be present and hold
+ suitable values to map all child nodes.
+
+Example:
+
+ uctl@118006c000000 {
+ compatible = "cavium,octeon-7130-sata-uctl";
+ reg = <0x11800 0x6c000000 0x0 0x100>;
+ ranges; /* Direct mapping */
+ dma-ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sata: sata@16c0000000000 {
+ compatible = "cavium,octeon-7130-ahci";
+ reg = <0x16c00 0x00000000 0x0 0x200>;
+ interrupt-parent = <&cibsata>;
+ interrupts = <2 4>; /* Bit: 2, level */
+ };
+ };