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authorKevin Cernekee <cernekee@gmail.com>2014-12-25 09:49:15 -0800
committerRalf Baechle <ralf@linux-mips.org>2015-04-01 17:21:41 +0200
commite5a6fcc05831b269be35ec266639d901b43cba78 (patch)
treeeda88fe484d7f780929eda786085d19d0f9eaec2 /Documentation/devicetree/bindings/mips
parent4b049a6b275db68c2c028937b89abd732dcdf536 (diff)
downloadlinux-e5a6fcc05831b269be35ec266639d901b43cba78.tar.gz
MIPS: BMIPS: Delete the irqchip driver from irq.c
BCM3384/BCM63xx can use the common drivers/irqchip/irq-bcm7120-l2.c for this purpose; BCM7xxx will use drivers/irqchip/irq-bcm7038-l1.c. We no longer need this code under arch/mips. [ralf@linux-mips.org: Fix conflicts.] Signed-off-by: Kevin Cernekee <cernekee@gmail.com> Cc: f.fainelli@gmail.com Cc: jaedon.shin@gmail.com Cc: abrestic@chromium.org Cc: tglx@linutronix.de Cc: jason@lakedaemon.net Cc: jogo@openwrt.org Cc: arnd@arndb.de Cc: computersforpeace@gmail.com Cc: linux-mips@linux-mips.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/8853/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mips')
-rw-r--r--Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt37
1 files changed, 0 insertions, 37 deletions
diff --git a/Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt b/Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt
deleted file mode 100644
index d4e0141d3620..000000000000
--- a/Documentation/devicetree/bindings/mips/brcm/bcm3384-intc.txt
+++ /dev/null
@@ -1,37 +0,0 @@
-* Interrupt Controller
-
-Properties:
-- compatible: "brcm,bcm3384-intc"
-
- Compatibility with BCM3384 and possibly other BCM33xx/BCM63xx SoCs.
-
-- reg: Address/length pairs for each mask/status register set. Length must
- be 8. If multiple register sets are specified, the first set will
- handle IRQ offsets 0..31, the second set 32..63, and so on.
-
-- interrupt-controller: This is an interrupt controller.
-
-- #interrupt-cells: Must be <1>. Just a simple IRQ offset; no level/edge
- or polarity configuration is possible with this controller.
-
-- interrupt-parent: This controller is cascaded from a MIPS CPU HW IRQ, or
- from another INTC.
-
-- interrupts: The IRQ on the parent controller.
-
-Example:
- periph_intc: periph_intc@14e00038 {
- compatible = "brcm,bcm3384-intc";
-
- /*
- * IRQs 0..31: mask reg 0x14e00038, status reg 0x14e0003c
- * IRQs 32..63: mask reg 0x14e00340, status reg 0x14e00344
- */
- reg = <0x14e00038 0x8 0x14e00340 0x8>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- interrupt-parent = <&cpu_intc>;
- interrupts = <4>;
- };