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authorAndrew Pinski <apinski@cavium.com>2016-02-24 17:44:57 -0800
committerCatalin Marinas <catalin.marinas@arm.com>2016-02-26 15:14:27 +0000
commit104a0c02e8b1936c049e18a6d4e4ab040fb61213 (patch)
tree405d1e134395cca369a63f3580f7f98a326c406e /arch/arm64/include
parent2f39b5f91eb4bccd786d194e70db1dccad784755 (diff)
downloadlinux-104a0c02e8b1936c049e18a6d4e4ab040fb61213.tar.gz
arm64: Add workaround for Cavium erratum 27456
On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become corrupted if it contains data for a non-current ASID. This patch implements the workaround (which invalidates the local icache when switching the mm) by using code patching. Signed-off-by: Andrew Pinski <apinski@cavium.com> Signed-off-by: David Daney <david.daney@cavium.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include')
-rw-r--r--arch/arm64/include/asm/cpufeature.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index be88aef01f3d..1497163213ed 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -33,8 +33,9 @@
#define ARM64_HAS_NO_HW_PREFETCH 8
#define ARM64_HAS_UAO 9
#define ARM64_ALT_PAN_NOT_UAO 10
+#define ARM64_WORKAROUND_CAVIUM_27456 12
-#define ARM64_NCAPS 11
+#define ARM64_NCAPS 13
#ifndef __ASSEMBLY__