summaryrefslogtreecommitdiff
path: root/arch/parisc/include/asm
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2015-11-04 11:30:22 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2015-11-04 11:30:22 -0800
commit14c79092909a52b6fd6394b6ad5e7756c4f9565e (patch)
treec9ab2a50aa00c8888cc90006a0e012782b0ccc19 /arch/parisc/include/asm
parent1b1050cdc5cdde43177b375b5f22dc070d45d8f8 (diff)
parenta01fece2e4185ac173abd16d10304d73d47ebf00 (diff)
downloadlinux-14c79092909a52b6fd6394b6ad5e7756c4f9565e.tar.gz
Merge branch 'parisc-4.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux
Pull parisc updates from Helge Deller: "The most important change is that we reduce L1_CACHE_BYTES to 16 bytes, for which a trivial patch for XPS in the network layer was needed. Then we wire up the sys_membarrier and userfaultfd syscalls and added two other small cleanups" * 'parisc-4.3-2' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux: parisc: Change L1_CACHE_BYTES to 16 net/xps: Fix calculation of initial number of xps queues parisc: reduce syslog debug output parisc: serial/mux: Convert to uart_console_device instead of open-coded parisc: Wire up userfaultfd syscall parisc: allocate sys_membarrier system call number
Diffstat (limited to 'arch/parisc/include/asm')
-rw-r--r--arch/parisc/include/asm/cache.h18
1 files changed, 5 insertions, 13 deletions
diff --git a/arch/parisc/include/asm/cache.h b/arch/parisc/include/asm/cache.h
index 47f11c707b65..3d0e17bcc8e9 100644
--- a/arch/parisc/include/asm/cache.h
+++ b/arch/parisc/include/asm/cache.h
@@ -7,20 +7,12 @@
/*
- * PA 2.0 processors have 64-byte cachelines; PA 1.1 processors have
- * 32-byte cachelines. The default configuration is not for SMP anyway,
- * so if you're building for SMP, you should select the appropriate
- * processor type. There is a potential livelock danger when running
- * a machine with this value set too small, but it's more probable you'll
- * just ruin performance.
+ * PA 2.0 processors have 64 and 128-byte L2 cachelines; PA 1.1 processors
+ * have 32-byte cachelines. The L1 length appears to be 16 bytes but this
+ * is not clearly documented.
*/
-#ifdef CONFIG_PA20
-#define L1_CACHE_BYTES 64
-#define L1_CACHE_SHIFT 6
-#else
-#define L1_CACHE_BYTES 32
-#define L1_CACHE_SHIFT 5
-#endif
+#define L1_CACHE_BYTES 16
+#define L1_CACHE_SHIFT 4
#ifndef __ASSEMBLY__