path: root/tools/perf/Documentation/perf-list.txt
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authorRobert Richter <>2012-08-07 19:43:15 +0200
committerArnaldo Carvalho de Melo <>2012-08-08 12:41:53 -0300
commit75bc5ca89827fe3f2399321b2920a30bcf658049 (patch)
tree795933aacb5c9f98613b3c4b8f44cd93f086a366 /tools/perf/Documentation/perf-list.txt
parent0cf260131c52f681533d17db6fd07545a3dc184e (diff)
perf list: Update documentation about raw event setup
It was missing that only certain bit fields are passed to the config value which confused users. Updating it. Signed-off-by: Robert Richter <> Cc: Ingo Molnar <> Link: Signed-off-by: Arnaldo Carvalho de Melo <>
Diffstat (limited to 'tools/perf/Documentation/perf-list.txt')
1 files changed, 6 insertions, 0 deletions
diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt
index ddc22525228d..232be519580a 100644
--- a/tools/perf/Documentation/perf-list.txt
+++ b/tools/perf/Documentation/perf-list.txt
@@ -15,6 +15,7 @@ DESCRIPTION
This command displays the symbolic event types which can be selected in the
various perf commands with the -e option.
@@ -44,6 +45,11 @@ layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Softwar
of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
+Note: Only the following bit fields can be set in x86 counter
+registers: event, umask, edge, inv, cmask. Esp. guest/host only and
+OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
If the Intel docs for a QM720 Core i7 describe an event as: