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authorAdrian Hunter <adrian.hunter@intel.com>2015-07-17 19:33:58 +0300
committerArnaldo Carvalho de Melo <acme@redhat.com>2015-08-24 17:49:43 -0300
commit0de802abd14abdf8cbbba28b421a1a00fa0939d5 (patch)
treeb5eb4fc861e0fe85cc14a2edd23168f01f890ce5 /tools/perf/arch
parentcc33618619cefc6d730cca3bb8e15311016a4da7 (diff)
downloadlinux-0de802abd14abdf8cbbba28b421a1a00fa0939d5.tar.gz
perf tools: Add Intel PT support for using CYC packets
CYC packets are a new Intel PT feature. CYC packets provide even finer grain timestamp information than MTC and TSC packets. A CYC packet contains the number of CPU cycles since the last CYC packet. Unlike MTC and TSC packets, CYC packets are only sent when another packet is also sent. Support for this feature is indicated by: /sys/bus/event_source/devices/intel_pt/caps/psb_cyc which contains "1" if the feature is supported and "0" otherwise. CYC packets can be requested using a PMU config term e.g. perf record -e intel_pt/cyc/u sleep 1 The frequency of CYC packets can also be specified. e.g. perf record -e intel_pt/cyc,cyc_thresh=2/u sleep 1 CYC packets are not requested by default. Valid cyc_thresh values are given by: /sys/bus/event_source/devices/intel_pt/caps/cycle_thresholds which contains a hexadecimal value, the bits of which represent valid values e.g. bit 2 set means value 2 is valid. The value represents the minimum number of CPU cycles that must have passed before a CYC packet can be sent. The number of CPU cycles is: 2 ^ (value - 1) e.g. value 4 means 8 CPU cycles must pass before a CYC packet can be sent. Note a CYC packet is still only sent when another packet is sent, not at, e.g. every 8 CPU cycles. If an invalid value is entered, the error message will give a list of valid values e.g. $ perf record -e intel_pt/cyc,cyc_thresh=15/u uname Invalid cyc_thresh for intel_pt. Valid values are: 0-12 tools/perf/Documentation/intel-pt.txt is updated in a later patch as there are a number of new features being added. For more information refer to the June 2015 or later Intel 64 and IA-32 Architectures SDM Chapter 36 Intel Processor Trace. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Link: http://lkml.kernel.org/r/1437150840-31811-24-git-send-email-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/arch')
-rw-r--r--tools/perf/arch/x86/util/intel-pt.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/tools/perf/arch/x86/util/intel-pt.c b/tools/perf/arch/x86/util/intel-pt.c
index a5de01dad868..2ca10d796c0b 100644
--- a/tools/perf/arch/x86/util/intel-pt.c
+++ b/tools/perf/arch/x86/util/intel-pt.c
@@ -475,6 +475,12 @@ static int intel_pt_validate_config(struct perf_pmu *intel_pt_pmu,
if (!evsel)
return 0;
+ err = intel_pt_val_config_term(intel_pt_pmu, "caps/cycle_thresholds",
+ "cyc_thresh", "caps/psb_cyc",
+ evsel->attr.config);
+ if (err)
+ return err;
+
err = intel_pt_val_config_term(intel_pt_pmu, "caps/mtc_periods",
"mtc_period", "caps/mtc",
evsel->attr.config);