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2016-06-24Merge branch 'akpm' (patches from Andrew)Linus Torvalds1-1/+1
Merge misc fixes from Andrew Morton: "Two weeks worth of fixes here" * emailed patches from Andrew Morton <>: (41 commits) init/main.c: fix initcall_blacklisted on ia64, ppc64 and parisc64 autofs: don't get stuck in a loop if vfs_write() returns an error mm/page_owner: avoid null pointer dereference tools/vm/slabinfo: fix spelling mistake: "Ocurrences" -> "Occurrences" fs/nilfs2: fix potential underflow in call to crc32_le oom, suspend: fix oom_reaper vs. oom_killer_disable race ocfs2: disable BUG assertions in reading blocks mm, compaction: abort free scanner if split fails mm: prevent KASAN false positives in kmemleak mm/hugetlb: clear compound_mapcount when freeing gigantic pages mm/swap.c: flush lru pvecs on compound page arrival memcg: css_alloc should return an ERR_PTR value on error memcg: mem_cgroup_migrate() may be called with irq disabled hugetlb: fix nr_pmds accounting with shared page tables Revert "mm: disable fault around on emulated access bit architecture" Revert "mm: make faultaround produce old ptes" mailmap: add Boris Brezillon's email mailmap: add Antoine Tenart's email mm, sl[au]b: add __GFP_ATOMIC to the GFP reclaim mask mm: mempool: kasan: don't poot mempool objects in quarantine ...
2016-06-24arm64: get rid of superfluous __GFP_REPEATMichal Hocko1-1/+1
__GFP_REPEAT has a rather weak semantic but since it has been introduced around 2.6.12 it has been ignored for low order allocations. {pte,pmd,pud}_alloc_one{_kernel}, late_pgtable_alloc use PGALLOC_GFP for __get_free_page (aka order-0). pgd_alloc is slightly more complex because it allocates from pgd_cache if PGD_SIZE != PAGE_SIZE and PGD_SIZE depends on the configuration (CONFIG_ARM64_VA_BITS, PAGE_SHIFT and CONFIG_PGTABLE_LEVELS). As per config PGTABLE_LEVELS int default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48 we should have the following options CONFIG_ARM64_VA_BITS:48 CONFIG_PGTABLE_LEVELS:4 PAGE_SIZE:4k size:4096 pages:1 CONFIG_ARM64_VA_BITS:48 CONFIG_PGTABLE_LEVELS:4 PAGE_SIZE:16k size:16 pages:1 CONFIG_ARM64_VA_BITS:48 CONFIG_PGTABLE_LEVELS:3 PAGE_SIZE:64k size:512 pages:1 CONFIG_ARM64_VA_BITS:47 CONFIG_PGTABLE_LEVELS:3 PAGE_SIZE:16k size:16384 pages:1 CONFIG_ARM64_VA_BITS:42 CONFIG_PGTABLE_LEVELS:2 PAGE_SIZE:64k size:65536 pages:1 CONFIG_ARM64_VA_BITS:39 CONFIG_PGTABLE_LEVELS:3 PAGE_SIZE:4k size:4096 pages:1 CONFIG_ARM64_VA_BITS:36 CONFIG_PGTABLE_LEVELS:2 PAGE_SIZE:16k size:16384 pages:1 All of them fit into a single page (aka order-0). This means that this flag has never been actually useful here because it has always been used only for PAGE_ALLOC_COSTLY requests. Link: Signed-off-by: Michal Hocko <> Acked-by: Will Deacon <> Cc: Catalin Marinas <> Signed-off-by: Andrew Morton <> Signed-off-by: Linus Torvalds <>
2016-06-22arm64: hibernate: Don't hibernate on systems with stuck CPUsJames Morse1-0/+6
Hibernate relies on cpu hotplug to prevent secondary cores executing the kernel text while it is being restored. Add a call to cpus_are_stuck_in_kernel() to determine if there are CPUs not counted by 'num_online_cpus()', and prevent hibernate in this case. Fixes: 82869ac57b5 ("arm64: kernel: Add support for hibernate/suspend-to-disk") Acked-by: Mark Rutland <> Signed-off-by: James Morse <> Signed-off-by: Will Deacon <>
2016-06-22arm64: smp: Add function to determine if cpus are stuck in the kernelJames Morse2-0/+30
kernel/smp.c has a fancy counter that keeps track of the number of CPUs it marked as not-present and left in cpu_park_loop(). If there are any CPUs spinning in here, features like kexec or hibernate may release them by overwriting this memory. This problem also occurs on machines using spin-tables to release secondary cores. After commit 44dbcc93ab67 ("arm64: Fix behavior of maxcpus=N") we bring all known cpus into the secondary holding pen, meaning this memory can't be re-used by kexec or hibernate. Add a function cpus_are_stuck_in_kernel() to determine if either of these cases have occurred. Signed-off-by: James Morse <> Acked-by: Mark Rutland <> Reviewed-by: Suzuki K Poulose <> Signed-off-by: Will Deacon <>
2016-06-21arm64: mm: remove page_mapping check in __sync_icache_dcacheShaokun Zhang1-4/+0
__sync_icache_dcache unconditionally skips the cache maintenance for anonymous pages, under the assumption that flushing is only required in the presence of D-side aliases [see 7249b79f6b4cc ("arm64: Do not flush the D-cache for anonymous pages")]. Unfortunately, this breaks migration of anonymous pages holding self-modifying code, where userspace cannot be reasonably expected to reissue maintenance instructions in response to a migration. This patch fixes the problem by removing the broken page_mapping(page) check from the cache syncing code, otherwise we may end up fetching and executing stale instructions from the PoU. Cc: Catalin Marinas <> Cc: Will Deacon <> Cc: Mark Rutland <> Cc: <> Reviewed-by: Catalin Marinas <> Signed-off-by: Shaokun Zhang <> Signed-off-by: Will Deacon <>
2016-06-21arm64: fix boot image dependencies to not generate invalid imagesMasahiro Yamada1-1/+1
I fixed boot image dependencies for arch/arm in commit 3939f3345050 ("ARM: 8418/1: add boot image dependencies to not generate invalid images"). I see a similar problem for arch/arm64; "make -jN Image Image.gz" would sometimes end up generating bad images where N > 1. Fix the dependency in arch/arm64/Makefile to avoid the race between "make Image" and "make Image.*". Acked-by: Catalin Marinas <> Signed-off-by: Masahiro Yamada <> Signed-off-by: Will Deacon <>
2016-06-21arm64: update ASID limitJean-Philippe Brucker1-3/+6
During a rollover, we mark the active ASID on each CPU as reserved, before allocating a new ID for the task that caused the rollover. This means that with N CPUs, we can only guarantee the new task to obtain a valid ASID if we have at least N+1 ASIDs. Update this limit in the initcall check. Note that this restriction was introduced by commit 8e648066 on the arch/arm side, which disallow re-using the previously active ASID on the local CPU, as it would introduce a TLB race. In addition, we only dispose of NUM_USER_ASIDS-1, since ASID 0 is reserved. Add this restriction as well. Signed-off-by: Jean-Philippe Brucker <> Signed-off-by: Will Deacon <>
2016-06-18Merge tag 'armsoc-fixes' of ↵Linus Torvalds2-2/+2
git:// Pull ARM SoC fixes from Olof Johansson: "Another batch of fixes for ARM SoC platforms. Most are smaller fixes. Two areas that are worth pointing out are: - OMAP had a handful of changes to voltage specs that caused a bit of churn, most of volume of change in this branch is due to this. - There are a couple of _rcuidle fixes from Paul that touch common code and came in through the OMAP tree since they were the ones who saw the problems. The rest is smaller changes across a handful of platforms" * tag 'armsoc-fixes' of git:// (36 commits) ARM: dts: STi: stih407-family: Disable reserved-memory co-processor nodes ARM: dts: am437x-sk-evm: Reduce i2c0 bus speed for tps65218 ARM: OMAP2+: timer: add probe for clocksources ARM: OMAP1: fix ams-delta FIQ handler to work with sparse IRQ memory: omap-gpmc: Fix omap gpmc EXTRADELAY timing arm: Use _rcuidle for smp_cross_call() tracepoints MAINTAINERS: Add myself as reviewer of ARM FSL/NXP ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON ARM: imx6ul: Fix Micrel PHY mask ARM: OMAP2+: Select OMAP_INTERCONNECT for SOC_AM43XX ARM: dts: DRA74x: fix DSS PLL2 addresses ARM: OMAP2: Enable Errata 430973 for OMAP3 ARM: dts: socfpga: Add missing PHY phandle ARM: dts: exynos: Fix port nodes names for Exynos5420 Peach Pit board ARM: dts: exynos: Fix port nodes names for Exynos5250 Snow board ARM: dts: sun6i: yones-toptech-bs1078-v2: Drop constraints on dc1sw regulator ARM: dts: sun6i: primo81: Drop constraints on dc1sw regulator ARM: dts: sunxi: Add OLinuXino Lime2 eMMC to the Makefile ...
2016-06-18Merge tag 'gpmc-omap-fixes-for-v4.7' of into ↵Olof Johansson1-1/+1
fixes OMAP-GPMC: Fixes for for v4.7-rc cycle: - Fix omap gpmc EXTRADELAY timing. The DT provided timings were wrongly used causing devices requiring extra delay timing to fail. * tag 'gpmc-omap-fixes-for-v4.7' of memory: omap-gpmc: Fix omap gpmc EXTRADELAY timing + Linux 4.7-rc3 Signed-off-by: Olof Johansson <>
2016-06-18Merge tag 'omap-for-v4.7/fixes-powedomain' of ↵Olof Johansson15-60/+116
git:// into fixes Fixes for omaps for v4.7-rc cycle: - Fix dra7 for hardware issues limiting L4Per and L3init power domains to on state. Without this the devices may not work correctly after some time of use because of asymmetric aging. And related to this, let's also remove the unusable states. - Always select omap interconnect for am43x as otherwise the am43x only configurations will not boot properly. This can happen easily for any product kernels that leave out other SoCs to save memory. - Fix DSS PLL2 addresses that have gone unused for now - Select erratum 430973 for omap3, this is now safe to do and can save quite a bit of debugging time for people who may have left it out. * tag 'omap-for-v4.7/fixes-powedomain' of git:// ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_mem_ret ARM: OMAP: DRA7: powerdomain data: Remove unused pwrsts_logic_ret ARM: OMAP: DRA7: powerdomain data: Set L3init and L4per to ON ARM: OMAP2+: Select OMAP_INTERCONNECT for SOC_AM43XX ARM: dts: DRA74x: fix DSS PLL2 addresses ARM: OMAP2: Enable Errata 430973 for OMAP3 + Linux 4.7-rc2 Signed-off-by: Olof Johansson <>
2016-06-16arm64: kgdb: Match pstate size with gdbserver protocolDaniel Thompson2-9/+50
Current versions of gdb do not interoperate cleanly with kgdb on arm64 systems because gdb and kgdb do not use the same register description. This patch modifies kgdb to work with recent releases of gdb (>= 7.8.1). Compatibility with gdb (after the patch is applied) is as follows: gdb-7.6 and earlier Ok gdb-7.7 series Works if user provides custom target description gdb-7.8(.0) Works if user provides custom target description gdb-7.8.1 and later Ok When commit 44679a4f142b ("arm64: KGDB: Add step debugging support") was introduced it was paired with a gdb patch that made an incompatible change to the gdbserver protocol. This patch was eventually merged into the gdb sources:;a=commit;h=a4d9ba85ec5597a6a556afe26b712e878374b9dd The change to the protocol was mostly made to simplify big-endian support inside the kernel gdb stub. Unfortunately the gdb project released gdb-7.7.x and gdb-7.8.0 before the protocol incompatibility was identified and reversed:;a=commit;h=bdc144174bcb11e808b4e73089b850cf9620a7ee This leaves us in a position where kgdb still uses the no-longer-used protocol; gdb-7.8.1, which restored the original behaviour, was released on 2014-10-29. I don't believe it is possible to detect/correct the protocol incompatiblity which means the kernel must take a view about which version of the gdb remote protocol is "correct". This patch takes the view that the original/current version of the protocol is correct and that version found in gdb-7.7.x and gdb-7.8.0 is anomalous. Signed-off-by: Daniel Thompson <> Signed-off-by: Will Deacon <>
2016-06-15arm64: spinlock: Ensure forward-progress in spin_unlock_waitWill Deacon1-3/+24
Rather than wait until we observe the lock being free (which might never happen), we can also return from spin_unlock_wait if we observe that the lock is now held by somebody else, which implies that it was unlocked but we just missed seeing it in that state. Furthermore, in such a scenario there is no longer a need to write back the value that we loaded, since we know that there has been a lock hand-off, which is sufficient to publish any stores prior to the unlock_wait because the ARm architecture ensures that a Store-Release instruction is multi-copy atomic when observed by a Load-Acquire instruction. The litmus test is something like: AArch64 { 0:X1=x; 0:X3=y; 1:X1=y; 2:X1=y; 2:X3=x; } P0 | P1 | P2 ; MOV W0,#1 | MOV W0,#1 | LDAR W0,[X1] ; STR W0,[X1] | STLR W0,[X1] | LDR W2,[X3] ; DMB SY | | ; LDR W2,[X3] | | ; exists (0:X2=0 /\ 2:X0=1 /\ 2:X2=0) where P0 is doing spin_unlock_wait, P1 is doing spin_unlock and P2 is doing spin_lock. Signed-off-by: Will Deacon <>
2016-06-15arm64: spinlock: fix spin_unlock_wait for LSE atomicsWill Deacon1-3/+7
Commit d86b8da04dfa ("arm64: spinlock: serialise spin_unlock_wait against concurrent lockers") fixed spin_unlock_wait for LL/SC-based atomics under the premise that the LSE atomics (in particular, the LDADDA instruction) are indivisible. Unfortunately, these instructions are only indivisible when used with the -AL (full ordering) suffix and, consequently, the same issue can theoretically be observed with LSE atomics, where a later (in program order) load can be speculated before the write portion of the atomic operation. This patch fixes the issue by performing a CAS of the lock once we've established that it's unlocked, in much the same way as the LL/SC code. Fixes: d86b8da04dfa ("arm64: spinlock: serialise spin_unlock_wait against concurrent lockers") Signed-off-by: Will Deacon <>
2016-06-15arm64: spinlock: order spin_{is_locked,unlock_wait} against local locksWill Deacon1-0/+7
spin_is_locked has grown two very different use-cases: (1) [The sane case] API functions may require a certain lock to be held by the caller and can therefore use spin_is_locked as part of an assert statement in order to verify that the lock is indeed held. For example, usage of assert_spin_locked. (2) [The insane case] There are two locks, where a CPU takes one of the locks and then checks whether or not the other one is held before accessing some shared state. For example, the "optimized locking" in ipc/sem.c. In the latter case, the sequence looks like: spin_lock(&sem->lock); if (!spin_is_locked(&sma->sem_perm.lock)) /* Access shared state */ and requires that the spin_is_locked check is ordered after taking the sem->lock. Unfortunately, since our spinlocks are implemented using a LDAXR/STXR sequence, the read of &sma->sem_perm.lock can be speculated before the STXR and consequently return a stale value. Whilst this hasn't been seen to cause issues in practice, PowerPC fixed the same issue in 51d7d5205d33 ("powerpc: Add smp_mb() to arch_spin_is_locked()") and, although we did something similar for spin_unlock_wait in d86b8da04dfa ("arm64: spinlock: serialise spin_unlock_wait against concurrent lockers") that doesn't actually take care of ordering against local acquisition of a different lock. This patch adds an smp_mb() to the start of our arch_spin_is_locked and arch_spin_unlock_wait routines to ensure that the lock value is always loaded after any other locks have been taken by the current CPU. Reported-by: Peter Zijlstra <> Signed-off-by: Will Deacon <>
2016-06-14arm64: mm: mark fault_info table constMark Rutland1-1/+1
Unlike the debug_fault_info table, we never intentionally alter the fault_info table at runtime, and all derived pointers are treated as const currently. Make the table const so that it can be placed in .rodata and protected from unintentional writes, as we do for the syscall tables. Signed-off-by: Mark Rutland <> Cc: Catalin Marinas <> Cc: Will Deacon <> Signed-off-by: Will Deacon <>
2016-06-14arm64: fix dump_instr when PAN and UAO are in useMark Rutland1-13/+13
If the kernel is set to show unhandled signals, and a user task does not handle a SIGILL as a result of an instruction abort, we will attempt to log the offending instruction with dump_instr before killing the task. We use dump_instr to log the encoding of the offending userspace instruction. However, dump_instr is also used to dump instructions from kernel space, and internally always switches to KERNEL_DS before dumping the instruction with get_user. When both PAN and UAO are in use, reading a user instruction via get_user while in KERNEL_DS will result in a permission fault, which leads to an Oops. As we have regs corresponding to the context of the original instruction abort, we can inspect this and only flip to KERNEL_DS if the original abort was taken from the kernel, avoiding this issue. At the same time, remove the redundant (and incorrect) comments regarding the order dump_mem and dump_instr are called in. Cc: Catalin Marinas <> Cc: James Morse <> Cc: Robin Murphy <> Cc: <> #4.6+ Signed-off-by: Mark Rutland <> Reported-by: Vladimir Murzin <> Tested-by: Vladimir Murzin <> Fixes: 57f4959bad0a154a ("arm64: kernel: Add support for User Access Override") Signed-off-by: Will Deacon <>
2016-06-08arm64: mm: always take dirty state from new pte in ptep_set_access_flagsWill Deacon1-1/+1
Commit 66dbd6e61a52 ("arm64: Implement ptep_set_access_flags() for hardware AF/DBM") ensured that pte flags are updated atomically in the face of potential concurrent, hardware-assisted updates. However, Alex reports that: | This patch breaks swapping for me. | In the broken case, you'll see either systemd cpu time spike (because | it's stuck in a page fault loop) or the system hang (because the | application owning the screen is stuck in a page fault loop). It turns out that this is because the 'dirty' argument to ptep_set_access_flags is always 0 for read faults, and so we can't use it to set PTE_RDONLY. The failing sequence is: 1. We put down a PTE_WRITE | PTE_DIRTY | PTE_AF pte 2. Memory pressure -> pte_mkold(pte) -> clear PTE_AF 3. A read faults due to the missing access flag 4. ptep_set_access_flags is called with dirty = 0, due to the read fault 5. pte is then made PTE_WRITE | PTE_DIRTY | PTE_AF | PTE_RDONLY (!) 6. A write faults, but pte_write is true so we get stuck The solution is to check the new page table entry (as would be done by the generic, non-atomic definition of ptep_set_access_flags that just calls set_pte_at) to establish the dirty state. Cc: <> # 4.3+ Fixes: 66dbd6e61a52 ("arm64: Implement ptep_set_access_flags() for hardware AF/DBM") Reviewed-by: Catalin Marinas <> Reported-by: Alexander Graf <> Tested-by: Alexander Graf <> Signed-off-by: Will Deacon <>
2016-06-03Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds1-0/+9
git:// Pull irq fixes from Thomas Gleixner: - a few simple fixes for fallout from the recent gic-v3 changes - a workaround for a Cavium thunderX erratum - a bugfix for the pic32 irqchip to make external interrupts work proper - a missing return value in the generic IPI management code * 'irq-urgent-for-linus' of git:// irqchip/irq-pic32-evic: Fix bug with external interrupts. irqchip/gicv3-its: numa: Enable workaround for Cavium thunderx erratum 23144 irqchip/gic-v3: Fix quiescence check in gic_enable_redist irqchip/gic-v3: Fix copy+paste mistakes in defines irqchip/gic-v3: Fix ICC_SGI1R_EL1.INTID decoding mask genirq: Fix missing return value in irq_destroy_ipi()
2016-06-03Merge tag 'arm64-fixes' of ↵Linus Torvalds13-44/+74
git:// Pull arm64 fixes from Will Deacon: "The main thing here is reviving hugetlb support using contiguous ptes, which we ended up reverting at the last minute in 4.5 pending a fix which went into the core mm/ code during the recent merge window. - Revert a previous revert and get hugetlb going with contiguous hints - Wire up missing compat syscalls - Enable CONFIG_SET_MODULE_RONX by default - Add missing line to our compat /proc/cpuinfo output - Clarify levels in our page table dumps - Fix booting with RANDOMIZE_TEXT_OFFSET enabled - Misc fixes to the ARM CPU PMU driver (refcounting, probe failure) - Remove some dead code and update a comment" * tag 'arm64-fixes' of git:// arm64: fix alignment when RANDOMIZE_TEXT_OFFSET is enabled arm64: move {PAGE,CONT}_SHIFT into Kconfig arm64: mm: dump: log span level arm64: update stale PAGE_OFFSET comment drivers/perf: arm_pmu: Avoid leaking pmu->irq_affinity on error drivers/perf: arm_pmu: Defer the setting of __oprofile_cpu_pmu drivers/perf: arm_pmu: Fix reference count of a device_node in of_pmu_irq_cfg arm64: report CPU number in bad_mode arm64: unistd32.h: wire up missing syscalls for compat tasks arm64: Provide "model name" in /proc/cpuinfo for PER_LINUX32 tasks arm64: enable CONFIG_SET_MODULE_RONX by default arm64: Remove orphaned __addr_ok() definition Revert "arm64: hugetlb: partial revert of 66b3923a1a0f"
2016-06-03arm64: dts: drop "arm,amba-bus" in favor of "simple-bus" part 2Masahiro Yamada2-2/+2
Tree-wide replacement was done by commit 2ef7d5f342c1 (ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"), but we have some new users of "arm,amba-bus" at Linux 4.7-rc1. Eliminate them now. Signed-off-by: Masahiro Yamada <> Acked-by: Heiko Stuebner <> Acked-by: Chanho Min <> Signed-off-by: Olof Johansson <>
2016-06-03arm64: fix alignment when RANDOMIZE_TEXT_OFFSET is enabledMark Rutland1-1/+3
With ARM64_64K_PAGES and RANDOMIZE_TEXT_OFFSET enabled, we hit the following issue on the boot: kernel BUG at arch/arm64/mm/mmu.c:480! Internal error: Oops - BUG: 0 [#1] PREEMPT SMP Modules linked in: CPU: 0 PID: 0 Comm: swapper Not tainted 4.6.0 #310 Hardware name: ARM Juno development board (r2) (DT) task: ffff000008d58a80 ti: ffff000008d30000 task.ti: ffff000008d30000 PC is at map_kernel_segment+0x44/0xb0 LR is at paging_init+0x84/0x5b0 pc : [<ffff000008c450b4>] lr : [<ffff000008c451a4>] pstate: 600002c5 Call trace: [<ffff000008c450b4>] map_kernel_segment+0x44/0xb0 [<ffff000008c451a4>] paging_init+0x84/0x5b0 [<ffff000008c42728>] setup_arch+0x198/0x534 [<ffff000008c40848>] start_kernel+0x70/0x388 [<ffff000008c401bc>] __primary_switched+0x30/0x74 Commit 7eb90f2ff7e3 ("arm64: cover the .head.text section in the .text segment mapping") removed the alignment between the .head.text and .text sections, and used the _text rather than the _stext interval for mapping the .text segment. Prior to this commit _stext was always section aligned and didn't cause any issue even when RANDOMIZE_TEXT_OFFSET was enabled. Since that alignment has been removed and _text is used to map the .text segment, we need ensure _text is always page aligned when RANDOMIZE_TEXT_OFFSET is enabled. This patch adds logic to TEXT_OFFSET fuzzing to ensure that the offset is always aligned to the kernel page size. To ensure this, we rely on the PAGE_SHIFT being available via Kconfig. Signed-off-by: Mark Rutland <> Reported-by: Sudeep Holla <> Cc: Ard Biesheuvel <> Cc: Catalin Marinas <> Cc: Will Deacon <> Fixes: 7eb90f2ff7e3 ("arm64: cover the .head.text section in the .text segment mapping") Signed-off-by: Will Deacon <>
2016-06-03arm64: move {PAGE,CONT}_SHIFT into KconfigMark Rutland2-10/+14
In some cases (e.g. the awk for CONFIG_RANDOMIZE_TEXT_OFFSET) we would like to make use of PAGE_SHIFT outside of code that can include the usual header files. Add a new CONFIG_ARM64_PAGE_SHIFT for this, likewise with ARM64_CONT_SHIFT for consistency. Signed-off-by: Mark Rutland <> Cc: Ard Biesheuvel <> Cc: Catalin Marinas <> Cc: Sudeep Holla <> Cc: Will Deacon <> Signed-off-by: Will Deacon <>
2016-06-03arm64: mm: dump: log span levelMark Rutland1-1/+7
The page table dump code logs spans of entries at the same level (pgd/pud/pmd/pte) which have the same attributes. While we log the (decoded) attributes, we don't log the level, which leaves the output ambiguous and/or confusing in some cases. For example: 0xffff800800000000-0xffff800980000000 6G RW NX SHD AF BLK UXN MEM/NORMAL If using 4K pages, this may describe a span of 6 1G block entries at the PGD/PUD level, or 3072 2M block entries at the PMD level. This patch adds the page table level to each output line, removing this ambiguity. For the example above, this will produce: 0xffffffc800000000-0xffffffc980000000 6G PUD RW NX SHD AF BLK UXN MEM/NORMAL When 3 level tables are in use, and we use the asm-generic/nopud.h definitions, the dump code treats each entry in the PGD as a 1 element table at the PUD level, and logs spans as being PUDs, which can be confusing. To counteract this, the "PUD" mnemonic is replaced with "PGD" when CONFIG_PGTABLE_LEVELS <= 3. Likewise for "PMD" when CONFIG_PGTABLE_LEVELS <= 2. Signed-off-by: Mark Rutland <> Cc: Catalin Marinas <> Cc: Huang Shijie <> Cc: Laura Abbott <> Cc: Steve Capper <> Cc: Will Deacon <> Signed-off-by: Will Deacon <>
2016-06-03arm64: update stale PAGE_OFFSET commentMark Rutland1-1/+2
Commit ab893fb9f1b17f02 ("arm64: introduce KIMAGE_VADDR as the virtual base of the kernel region") logically split KIMAGE_VADDR from PAGE_OFFSET, and since commit f9040773b7bbbd9e ("arm64: move kernel image to base of vmalloc area") the two have been distinct values. Unfortunately, neither commit updated the comment above these definitions, which now erroneously states that PAGE_OFFSET is the start of the kernel image rather than the start of the linear mapping. This patch fixes said comment, and introduces an explanation of KIMAGE_VADDR. Signed-off-by: Mark Rutland <> Cc: Will Deacon <> Cc: Catalin Marinas <> Cc: Marc Zyngier <> Signed-off-by: Will Deacon <>
2016-06-03arm64: report CPU number in bad_modeMark Rutland1-2/+3
If we take an exception we don't expect (e.g. SError), we report this in the bad_mode handler with pr_crit. Depending on the configured log level, we may or may not log additional information in functions called subsequently. Notably, the messages in dump_stack (including the CPU number) are printed with KERN_DEFAULT and may not appear. Some exceptions have an IMPLEMENTATION DEFINED ESR_ELx.ISS encoding, and knowing the CPU number is crucial to correctly decode them. To ensure that this is always possible, we should log the CPU number along with the ESR_ELx value, so we are not reliant on subsequent logs or additional printk configuration options. This patch logs the CPU number in bad_mode such that it is possible for a developer to decode these exceptions, provided access to sufficient documentation. Signed-off-by: Mark Rutland <> Reported-by: Al Grant <> Cc: Catalin Marinas <> Cc: Dave Martin <> Cc: Robin Murphy <> Cc: Will Deacon <> Signed-off-by: Will Deacon <>
2016-06-02irqchip/gicv3-its: numa: Enable workaround for Cavium thunderx erratum 23144Ganapatrao Kulkarni1-0/+9
The erratum fixes the hang of ITS SYNC command by avoiding inter node io and collections/cpu mapping on thunderx dual-socket platform. This fix is only applicable for Cavium's ThunderX dual-socket platform. Reviewed-by: Robert Richter <> Signed-off-by: Ganapatrao Kulkarni <> Signed-off-by: Robert Richter <> Signed-off-by: Marc Zyngier <>
2016-06-01arm64: unistd32.h: wire up missing syscalls for compat tasksWill Deacon2-1/+9
We're missing entries for mlock2, copy_file_range, preadv2 and pwritev2 in our compat syscall table, so hook them up. Only the last two need compat wrappers. Signed-off-by: Will Deacon <>
2016-05-31arm64: Provide "model name" in /proc/cpuinfo for PER_LINUX32 tasksCatalin Marinas2-3/+9
This patch brings the PER_LINUX32 /proc/cpuinfo format more in line with the 32-bit ARM one by providing an additional line: model name : ARMv8 Processor rev X (v8l) Cc: <> Acked-by: Will Deacon <> Signed-off-by: Catalin Marinas <> Signed-off-by: Will Deacon <>
2016-05-31arm64: KVM: vgic-v3: Relax synchronization when SRE==1Marc Zyngier1-7/+16
The GICv3 backend of the vgic is quite barrier heavy, in order to ensure synchronization of the system registers and the memory mapped view for a potential GICv2 guest. But when the guest is using a GICv3 model, there is absolutely no need to execute all these heavy barriers, and it is actually beneficial to avoid them altogether. This patch makes the synchonization conditional, and ensures that we do not change the EL1 SRE settings if we do not need to. Reviewed-by: Christoffer Dall <> Signed-off-by: Marc Zyngier <> Signed-off-by: Christoffer Dall <>
2016-05-31arm64: KVM: vgic-v3: Prevent the guest from messing with ICC_SRE_EL1Marc Zyngier1-4/+2
Both our GIC emulations are "strict", in the sense that we either emulate a GICv2 or a GICv3, and not a GICv3 with GICv2 legacy support. But when running on a GICv3 host, we still allow the guest to tinker with the ICC_SRE_EL1 register during its time slice: it can switch SRE off, observe that it is off, and yet on the next world switch, find the SRE bit to be set again. Not very nice. An obvious solution is to always trap accesses to ICC_SRE_EL1 (by clearing ICC_SRE_EL2.Enable), and to let the handler return the programmed value on a read, or ignore the write. That way, the guest can always observe that our GICv3 is SRE==1 only. Reviewed-by: Christoffer Dall <> Signed-off-by: Marc Zyngier <> Signed-off-by: Christoffer Dall <>
2016-05-31arm64: KVM: Make ICC_SRE_EL1 access return the configured SRE valueMarc Zyngier1-1/+12
When we trap ICC_SRE_EL1, we handle it as RAZ/WI. It would be more correct to actual make it RO, and return the configured value when read. Reviewed-by: Christoffer Dall <> Signed-off-by: Marc Zyngier <> Signed-off-by: Christoffer Dall <>
2016-05-31KVM: arm/arm64: vgic-v3: Clear all dirty LRsChristoffer Dall1-4/+3
When saving the state of the list registers, it is critical to reset them zero, as we could otherwise leave unexpected EOI interrupts pending for virtual level interrupts. Cc: # v4.6+ Signed-off-by: Christoffer Dall <> Signed-off-by: Marc Zyngier <>
2016-05-31arm64: enable CONFIG_SET_MODULE_RONX by defaultMark Rutland1-12/+13
The SET_MODULE_RONX protections are effectively the same as the DEBUG_RODATA protections we enabled by default back in commit 57efac2f7108e325 ("arm64: enable CONFIG_DEBUG_RODATA by default"). It seems unusual to have one but not the other. As evidenced by the help text, the rationale appears to be that SET_MODULE_RONX interacts poorly with tracing and patching, but both of these make use of the insn framework, which takes SET_MODULE_RONX into account. Any remaining issues are bugs which should be fixed regardless of the default state of the option. This patch enables DEBUG_SET_MODULE_RONX by default, and replaces the help text with a new wording derived from the DEBUG_RODATA help text, which better describes the functionality. Previously, the DEBUG_RODATA entry was inconsistently indented with spaces, which are replaced with tabs as with the other Kconfig entries. Additionally, the wording of recommended defaults is made consistent for all options. These are placed in a new paragraph, unquoted, as a full sentence (with a period/full stop) as this appears to be the most common form per $(git grep 'in doubt'). Cc: Catalin Marinas <> Cc: Laura Abbott <> Acked-by: Kees Cook <> Acked-by: Ard Biesheuvel <> Signed-off-by: Mark Rutland <> Signed-off-by: Will Deacon <>
2016-05-31arm64: Remove orphaned __addr_ok() definitionRobin Murphy1-13/+0
Since commit 12a0ef7b0ac3 ("arm64: use generic strnlen_user and strncpy_from_user functions"), the definition of __addr_ok() has been languishing unused; eradicate the sucker. CC: Catalin Marinas <> Signed-off-by: Robin Murphy <> Signed-off-by: Will Deacon <>
2016-05-31Revert "arm64: hugetlb: partial revert of 66b3923a1a0f"Will Deacon1-0/+14
This reverts commit ff7925848b50050732ac0401e0acf27e8b241d7b. Now that the contiguous-hint hugetlb regression has been debugged and fixed upstream by 66ee95d16a7f ("mm: exclude HugeTLB pages from THP page_mapped() logic"), we can revert the previous partial revert of this feature. Signed-off-by: Will Deacon <>
2016-05-27Merge tag 'for-linus' of git:// Torvalds5-1/+29
Pull second batch of KVM updates from Radim Krčmář: "General: - move kvm_stat tool from QEMU repo into tools/kvm/kvm_stat (kvm_stat had nothing to do with QEMU in the first place -- the tool only interprets debugfs) - expose per-vm statistics in debugfs and support them in kvm_stat (KVM always collected per-vm statistics, but they were summarised into global statistics) x86: - fix dynamic APICv (VMX was improperly configured and a guest could access host's APIC MSRs, CVE-2016-4440) - minor fixes ARM changes from Christoffer Dall: - new vgic reimplementation of our horribly broken legacy vgic implementation. The two implementations will live side-by-side (with the new being the configured default) for one kernel release and then we'll remove the legacy one. - fix for a non-critical issue with virtual abort injection to guests" * tag 'for-linus' of git:// (70 commits) tools: kvm_stat: Add comments tools: kvm_stat: Introduce pid monitoring KVM: Create debugfs dir and stat files for each VM MAINTAINERS: Add kvm tools tools: kvm_stat: Powerpc related fixes tools: Add kvm_stat man page tools: Add kvm_stat vm monitor script kvm:vmx: more complete state update on APICv on/off KVM: SVM: Add more SVM_EXIT_REASONS KVM: Unify traced vector format svm: bitwise vs logical op typo KVM: arm/arm64: vgic-new: Synchronize changes to active state KVM: arm/arm64: vgic-new: enable build KVM: arm/arm64: vgic-new: implement mapped IRQ handling KVM: arm/arm64: vgic-new: Wire up irqfd injection KVM: arm/arm64: vgic-new: Add vgic_v2/v3_enable KVM: arm/arm64: vgic-new: vgic_init: implement map_resources KVM: arm/arm64: vgic-new: vgic_init: implement vgic_init KVM: arm/arm64: vgic-new: vgic_init: implement vgic_create KVM: arm/arm64: vgic-new: vgic_init: implement kvm_vgic_hyp_init ...
2016-05-25Merge branch 'perf-urgent-for-linus' of ↵Linus Torvalds1-7/+7
git:// Pull perf updates from Ingo Molnar: "Mostly tooling and PMU driver fixes, but also a number of late updates such as the reworking of the call-chain size limiting logic to make call-graph recording more robust, plus tooling side changes for the new 'backwards ring-buffer' extension to the perf ring-buffer" * 'perf-urgent-for-linus' of git:// (34 commits) perf record: Read from backward ring buffer perf record: Rename variable to make code clear perf record: Prevent reading invalid data in record__mmap_read perf evlist: Add API to pause/resume perf trace: Use the ptr->name beautifier as default for "filename" args perf trace: Use the fd->name beautifier as default for "fd" args perf report: Add srcline_from/to branch sort keys perf evsel: Record fd into perf_mmap perf evsel: Add overwrite attribute and check write_backward perf tools: Set buildid dir under symfs when --symfs is provided perf trace: Only auto set call-graph to "dwarf" when syscalls are being traced perf annotate: Sort list of recognised instructions perf annotate: Fix identification of ARM blt and bls instructions perf tools: Fix usage of max_stack sysctl perf callchain: Stop validating callchains by the max_stack sysctl perf trace: Fix exit_group() formatting perf top: Use machine->kptr_restrict_warned perf trace: Warn when trying to resolve kernel addresses with kptr_restrict=1 perf machine: Do not bail out if not managing to read ref reloc symbol perf/x86/intel/p4: Trival indentation fix, remove space ...
2016-05-25Merge git:// Torvalds1-0/+2
Pull watchdog updates from Wim Van Sebroeck: - add support for Fintek F81865 Super-IO chip - add support for watchdogs (RWDT and SWDT) found on RCar Gen3 based SoCs from Renesas - octeon: Handle the FROZEN hot plug notifier actions - f71808e_wdt fixes and cleanups - some small improvements in code and documentation * git:// MAINTAINERS: Add file patterns for watchdog device tree bindings Documentation: Add ebc-c384_wdt watchdog-parameters.txt entry watchdog: shwdt: Use setup_timer() watchdog: cpwd: Use setup_timer() arm64: defconfig: enable Renesas Watchdog Timer watchdog: renesas-wdt: add driver watchdog: remove error message when unable to allocate watchdog device watchdog: f71808e_wdt: Fix WDTMOUT_STS register read watchdog: f71808e_wdt: Fix typo watchdog: f71808e_wdt: Add F81865 support watchdog: sp5100_tco: properly check for new register layouts watchdog: core: Fix circular locking dependency watchdog: core: fix trivial typo in a comment watchdog: hpwdt: Adjust documentation to match latest kernel module parameters. watchdog: imx2_wdt: add external reset support via dt prop watchdog: octeon: Handle the FROZEN hot plug notifier actions. watchdog: qcom: Report reboot reason
2016-05-24Merge tag 'armsoc-late' of ↵Linus Torvalds1-55/+68
git:// Pull ARM SoC late DT updates from Arnd Bergmann: "This is a collection of a few late fixes and other misc stuff that had dependencies on things being merged from other trees. The Renesas R-Car power domain handling, and the Nvidia Tegra USB support both hand notable changes that required changing the DT binding in a way that only provides compatibility with old DT blobs on new kernels but not vice versa. As a consequence, the DT changes are based on top of the driver changes and are now in this branch. For NXP i.MX and Samsung Exynos, the changes in here depend on other changes that got merged through the clk maintainer tree" * tag 'armsoc-late' of git:// (35 commits) ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3 ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250 ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk ARM: dts: exynos: Add DMC bus node for Exynos3250 ARM: tegra: Enable XUSB on Nyan ARM: tegra: Enable XUSB on Jetson TK1 ARM: tegra: Enable XUSB on Venice2 ARM: tegra: Add Tegra124 XUSB controller ARM: tegra: Move Tegra124 to the new XUSB pad controller binding ARM: dts: r8a7794: Use SYSC "always-on" PM Domain ARM: dts: r8a7793: Use SYSC "always-on" PM Domain ...
2016-05-24Merge tag 'asm-generic-4.7' of ↵Linus Torvalds1-0/+3
git:// Pull asm-generic cleanup from Arnd Bergmann: "I have only one patch for asm-generic in this release, this one is from James Hogan and updates the generic system call table for renameat2 so we don't need to provide both renameat and renameat2 in newly added architectures" * tag 'asm-generic-4.7' of git:// asm-generic: Drop renameat syscall from default list
2016-05-24Merge tag 'kvm-arm-for-4-7-take2' of ↵Paolo Bonzini5-1/+29
git:// into kvm-next KVM/ARM Changes for v4.7 take 2 "The GIC is dead; Long live the GIC" This set of changes include the new vgic, which is a reimplementation of our horribly broken legacy vgic implementation. The two implementations will live side-by-side (with the new being the configured default) for one kernel release and then we'll remove it. Also fixes a non-critical issue with virtual abort injection to guests.
2016-05-23vdso: make arch_setup_additional_pages wait for mmap_sem for write killableMichal Hocko1-2/+4
most architectures are relying on mmap_sem for write in their arch_setup_additional_pages. If the waiting task gets killed by the oom killer it would block oom_reaper from asynchronous address space reclaim and reduce the chances of timely OOM resolving. Wait for the lock in the killable mode and return with EINTR if the task got killed while waiting. Signed-off-by: Michal Hocko <> Acked-by: Andy Lutomirski <> [x86 vdso] Acked-by: Vlastimil Babka <> Signed-off-by: Andrew Morton <> Signed-off-by: Linus Torvalds <>
2016-05-20exit_thread: remove empty bodiesJiri Slaby1-7/+0
Define HAVE_EXIT_THREAD for archs which want to do something in exit_thread. For others, let's define exit_thread as an empty inline. This is a cleanup before we change the prototype of exit_thread to accept a task parameter. [ fix mips] Signed-off-by: Jiri Slaby <> Cc: "David S. Miller" <> Cc: "H. Peter Anvin" <> Cc: "James E.J. Bottomley" <> Cc: Aurelien Jacquiot <> Cc: Benjamin Herrenschmidt <> Cc: Catalin Marinas <> Cc: Chen Liqin <> Cc: Chris Metcalf <> Cc: Chris Zankel <> Cc: David Howells <> Cc: Fenghua Yu <> Cc: Geert Uytterhoeven <> Cc: Guan Xuetao <> Cc: Haavard Skinnemoen <> Cc: Hans-Christian Egtvedt <> Cc: Heiko Carstens <> Cc: Helge Deller <> Cc: Ingo Molnar <> Cc: Ivan Kokshaysky <> Cc: James Hogan <> Cc: Jeff Dike <> Cc: Jesper Nilsson <> Cc: Jiri Slaby <> Cc: Jonas Bonn <> Cc: Koichi Yasutake <> Cc: Lennox Wu <> Cc: Ley Foon Tan <> Cc: Mark Salter <> Cc: Martin Schwidefsky <> Cc: Matt Turner <> Cc: Max Filippov <> Cc: Michael Ellerman <> Cc: Michal Simek <> Cc: Mikael Starvik <> Cc: Paul Mackerras <> Cc: Peter Zijlstra <> Cc: Ralf Baechle <> Cc: Rich Felker <> Cc: Richard Henderson <> Cc: Richard Kuo <> Cc: Richard Weinberger <> Cc: Russell King <> Cc: Steven Miao <> Cc: Thomas Gleixner <> Cc: Tony Luck <> Cc: Vineet Gupta <> Cc: Will Deacon <> Cc: Yoshinori Sato <> Signed-off-by: Andrew Morton <> Signed-off-by: Linus Torvalds <>
2016-05-20KVM: arm/arm64: vgic-new: Synchronize changes to active stateChristoffer Dall1-0/+2
When modifying the active state of an interrupt via the MMIO interface, we should ensure that the write has the intended effect. If a guest sets an interrupt to active, but that interrupt is already flushed into a list register on a running VCPU, then that VCPU will write the active state back into the struct vgic_irq upon returning from the guest and syncing its state. This is a non-benign race, because the guest can observe that an interrupt is not active, and it can have a reasonable expectations that other VCPUs will not ack any IRQs, and then set the state to active, and expect it to stay that way. Currently we are not honoring this case. Thefore, change both the SACTIVE and CACTIVE mmio handlers to stop the world, change the irq state, potentially queue the irq if we're setting it to active, and then continue. We take this chance to slightly optimize these functions by not stopping the world when touching private interrupts where there is inherently no possible race. Signed-off-by: Christoffer Dall <>
2016-05-20KVM: arm/arm64: vgic-new: enable buildAndre Przywara2-0/+19
Now that the new VGIC implementation has reached feature parity with the old one, add the new files to the build system and add a Kconfig option to switch between the two versions. We set the default to the new version to get maximum test coverage, in case people experience problems they can switch back to the old behaviour if needed. Signed-off-by: Andre Przywara <> Acked-by: Christoffer Dall <>
2016-05-20KVM: arm/arm64: Provide functionality to pause and resume a guestChristoffer Dall1-0/+4
For some rare corner cases in our VGIC emulation later we have to stop the guest to make sure the VGIC state is consistent. Provide the necessary framework to pause and resume a guest. Signed-off-by: Christoffer Dall <> Signed-off-by: Andre Przywara <>
2016-05-20KVM: arm/arm64: Export mmio_read/write_busChristoffer Dall1-0/+3
Rename mmio_{read,write}_bus to kvm_mmio_{read,write}_bus and export them out of mmio.c. This will be needed later for the new VGIC implementation. Signed-off-by: Christoffer Dall <> Signed-off-by: Andre Przywara <> Acked-by: Marc Zyngier <> Reviewed-by: Andre Przywara <>
2016-05-20kvm: arm64: Fix EC field in inject_abt64Matt Evans1-1/+1
The EC field of the constructed ESR is conditionally modified by ORing in ESR_ELx_EC_DABT_LOW for a data abort. However, ESR_ELx_EC_SHIFT is missing from this condition. Signed-off-by: Matt Evans <> Acked-by: Marc Zyngier <> Cc: <> Signed-off-by: Christoffer Dall <>
2016-05-20Merge tag 'perf-core-for-mingo-20160516' of ↵Ingo Molnar1-7/+7
git:// into perf/core Pull perf/core improvements and fixes from Arnaldo Carvalho de Melo: User visible changes: - Honour the kernel.perf_event_max_stack knob more precisely by not counting PERF_CONTEXT_{KERNEL,USER} when deciding when to stop adding entries to the perf_sample->ip_callchain[] array (Arnaldo Carvalho de Melo) - Fix identation of 'stalled-backend-cycles' in 'perf stat' (Namhyung Kim) - Update runtime using 'cpu-clock' event in 'perf stat' (Namhyung Kim) - Use 'cpu-clock' for cpu targets in 'perf stat' (Namhyung Kim) - Avoid fractional digits for integer scales in 'perf stat' (Andi Kleen) - Store vdso buildid unconditionally, as it appears in callchains and we're not checking those when creating the build-id table, so we end up not being able to resolve VDSO symbols when doing analysis on a different machine than the one where recording was done, possibly of a different arch even (arm -> x86_64) (He Kuang) Infrastructure changes: - Generalize max_stack sysctl handler, will be used for configuring multiple kernel knobs related to callchains (Arnaldo Carvalho de Melo) Cleanups: - Introduce DSO__NAME_KALLSYMS and DSO__NAME_KCORE, to stop using open coded strings (Masami Hiramatsu) Signed-off-by: Arnaldo Carvalho de Melo <> Signed-off-by: Ingo Molnar <>
2016-05-19Merge branch 'akpm' (patches from Andrew)Linus Torvalds2-5/+1
Merge updates from Andrew Morton: - fsnotify fix - poll() timeout fix - a few scripts/ tweaks - debugobjects updates - the (small) ocfs2 queue - Minor fixes to kernel/padata.c - Maybe half of the MM queue * emailed patches from Andrew Morton <>: (117 commits) mm, page_alloc: restore the original nodemask if the fast path allocation failed mm, page_alloc: uninline the bad page part of check_new_page() mm, page_alloc: don't duplicate code in free_pcp_prepare mm, page_alloc: defer debugging checks of pages allocated from the PCP mm, page_alloc: defer debugging checks of freed pages until a PCP drain cpuset: use static key better and convert to new API mm, page_alloc: inline pageblock lookup in page free fast paths mm, page_alloc: remove unnecessary variable from free_pcppages_bulk mm, page_alloc: pull out side effects from free_pages_check mm, page_alloc: un-inline the bad part of free_pages_check mm, page_alloc: check multiple page fields with a single branch mm, page_alloc: remove field from alloc_context mm, page_alloc: avoid looking up the first zone in a zonelist twice mm, page_alloc: shortcut watermark checks for order-0 pages mm, page_alloc: reduce cost of fair zone allocation policy retry mm, page_alloc: shorten the page allocator fast path mm, page_alloc: check once if a zone has isolated pageblocks mm, page_alloc: move __GFP_HARDWALL modifications out of the fastpath mm, page_alloc: simplify last cpupid reset mm, page_alloc: remove unnecessary initialisation from __alloc_pages_nodemask() ...