path: root/drivers
AgeCommit message (Collapse)AuthorFilesLines
2015-05-23vcsm: Add ioctl for custom cache flushingpopcornmix1-0/+49
2015-05-21vchiq: Change logging level for inbound dataPhil Elwell1-1/+1
2015-05-20i2c-bcm2708: When using DT, leave the GPIO setup to pinctrlPhil Elwell1-1/+2
2015-05-19bcm2708: vchiq: Add Device Tree supportNoralf Trønnes4-98/+79
Turn vchiq into a driver and stop hardcoding resources. Use devm_* functions in probe path to simplify cleanup. A global variable is used to hold the register address. This is done to keep this patch as small as possible. Also make available on ARCH_BCM2835. Based on work by Lubomir Rintel. Signed-off-by: Noralf Trønnes <>
2015-05-18fbdev: bcm2708_fb: Add ARCH_BCM2835 supportNoralf Trønnes1-5/+9
Add Device Tree support. Pass the device to dma_alloc_coherent() in order to get the correct bus address on ARCH_BCM2835. Use the new DMA legacy API header file. Including <mach/platform.h> is not necessary. Signed-off-by: Noralf Trønnes <>
2015-05-18usb: dwc_otg: Don't use dma_to_virt()Noralf Trønnes1-4/+5
Commit 6ce0d20 changes dma_to_virt() which breaks this driver. Open code the old dma_to_virt() implementation to work around this. Limit the use of __bus_to_virt() to cases where transfer_buffer_length is set and transfer_buffer is not set. This is done to increase the chance that this driver will also work on ARCH_BCM2835. transfer_buffer should not be NULL if the length is set, but the comment in the code indicates that there are situations where this might happen. drivers/usb/isp1760/isp1760-hcd.c also has a similar comment pointing to a possible: 'usb storage / SCSI bug'. Signed-off-by: Noralf Trønnes <>
2015-05-18bcm2835-mmc: Round up the overclock, so 62 works for 62.5MhzPhil Elwell1-2/+5
Also only warn once for each overclock setting.
2015-05-18bcm2835-sdhost: Round up the overclock, so 62 works for 62.5MhzPhil Elwell1-2/+5
Also only warn once for each overclock setting.
2015-05-18dmaengine: bcm2708: set residue_granularity fieldMatthias Reichl1-0/+2
bcm2708-dmaengine supports residue reporting at burst level but didn't report this via the residue_granularity field. Without this field set properly we get playback issues with I2S cards.
2015-05-18bcm2835-mmc: Adding overclocking optionPhil Elwell1-3/+22
Allow a different clock speed to be substitued for a requested 50MHz. This option is exposed using the "overclock_50" DT parameter. Note that the mmc interface is restricted to EVEN integer divisions of 250MHz, and the highest sensible option is 63 (250/4 = 62.5), the next being 125 (250/2) which is much too high. Use at your own risk.
2015-05-18bcm2835-sdhost: Adding overclocking optionPhil Elwell1-2/+15
Allow a different clock speed to be substitued for a requested 50MHz. This option is exposed using the "overclock_50" DT parameter. Note that the sdhost interface is restricted to integer divisions of core_freq, and the highest sensible option for a core_freq of 250MHz is 84 (250/3 = 83.3MHz), the next being 125 (250/2) which is much too high. Use at your own risk.
2015-05-18bcm2835-sdhost: Error handling fix, and code clarificationPhil Elwell1-5/+6
2015-05-18rpi-ft5406: Add touchscreen driver for pi LCD displayGordon Hollingworth3-0/+266
2015-05-18mailbox: bcm2708-vcio: Check the correct status register before writingNoralf Trønnes1-1/+2
With the VC reader blocked and the ARM writing, MAIL0_STA reads empty permanently while MAIL1_STA goes from empty (0x40000000) to non-empty (0x00000001-0x00000007) to full (0x80000008). Suggested-by: Phil Elwell <> Signed-off-by: Noralf Trønnes <>
2015-05-18mailbox: bcm2708-vcio: Allocation does not need to be atomicNoralf Trønnes1-1/+1
No need to do atomic allocation in a context that can sleep. Signed-off-by: Noralf Trønnes <>
2015-05-18BCM270x: Use bcm2708-vcioNoralf Trønnes5-5/+5
Use bcm2708-vcio instead of the arch version. Change affected drivers to use linux/platform_data/mailbox-bcm2708.h Signed-off-by: Noralf Trønnes <>
2015-05-18mailbox: bcm2708: Add bcm2708-vcioNoralf Trønnes3-0/+434
Copy the arch vcio.c driver to drivers/mailbox. This is done to make it available on ARCH_BCM2835. Signed-off-by: Noralf Trønnes <>
2015-05-18video: fbdev: bcm2708_fb: Don't panic on errorNoralf Trønnes1-3/+5
No need to panic the kernel if the video driver fails. Just print a message and return an error. Signed-off-by: Noralf Trønnes <>
2015-05-18bcm2835-mmc: Add range of debug options for slowing things downpopcornmix2-14/+32
bcm2835-mmc: Add option to disable some delays bcm2835-mmc: Add option to disable MMC_QUIRK_BLK_NO_CMD23 bcm2835-mmc: Default to disabling MMC_QUIRK_BLK_NO_CMD23
2015-05-18bcm2835-mmc: Add locks when accessing sdhost registerspopcornmix1-3/+17
2015-05-18dmaengine: increment privatecnt when using dma_get_any_slave_channelChristopher Freeman1-0/+4
Channels allocated via dma_get_any_slave_channel were not increasing the counter tracking private allocations. When these channels were released, privatecnt may erroneously fall to zero. The DMA device would then lose its DMA_PRIVATE cap and fail to allocate future private channels (via private_candidate) as any allocations still outstanding would incorrectly be seen as public allocations. Signed-off-by: Christopher Freeman <> Signed-off-by: Vinod Koul <>
2015-05-18mmc: bcm2835-mmc: Make available on ARCH_BCM2835Noralf Trønnes1-1/+1
Make the bcm2835-mmc driver available for use on ARCH_BCM2835. Signed-off-by: Noralf Trønnes <>
2015-05-18dmaengine: bcm2708: Merge with arch dma.c driver and disable dma.cNoralf Trønnes2-18/+324
Merge the legacy DMA API driver with bcm2708-dmaengine. This is done so we can use bcm2708_fb on ARCH_BCM2835 (mailbox driver is also needed). Changes to the dma.c code: - Use BIT() macro. - Cutdown some comments to one line. - Add mutex to vc_dmaman and use this, since the dev lock is locked during probing of the engine part. - Add global g_dmaman variable since drvdata is used by the engine part. - Restructure for readability: vc_dmaman_chan_alloc() vc_dmaman_chan_free() bcm_dma_chan_free() - Restructure bcm_dma_chan_alloc() to simplify error handling. - Use device irq resources instead of hardcoded bcm_dma_irqs table. - Remove dev_dmaman_register() and code it directly. - Remove dev_dmaman_deregister() and code it directly. - Simplify bcm_dmaman_probe() using devm_* functions. - Get dmachans from DT if available. - Keep 'dma.dmachans' module argument name for backwards compatibility. Make it available on ARCH_BCM2835 as well. Signed-off-by: Noralf Trønnes <>
2015-05-18Adding bcm2835-sdhost driver, and an overlay to enable itPhil Elwell3-0/+1696
BCM2835 has two SD card interfaces. This driver uses the other one.
2015-05-18Add blk_pos parameter to mmc multi_io_quirk callbackPhil Elwell4-3/+10
2015-05-18bcm2708-dmaengine: Add debug optionspopcornmix1-1/+7
2015-05-18smsc95xx: Disable turbo mode by defaultpopcornmix1-1/+1
2015-05-18smsx95xx: fix crimes against truesizeSteve Glendinning1-2/+0
smsc95xx is adjusting truesize when it shouldn't, and following a recent patch from Eric this is now triggering warnings. This patch stops smsc95xx from changing truesize. Signed-off-by: Steve Glendinning <>
2015-05-18spi: bcm2835: change timeout of polling driver to 1sMartin Sperl1-3/+2
The way that the timeout code is written in the polling function the timeout does also trigger when interrupted or rescheduled while in the polling loop. This patch changes the timeout from effectively 20ms (=2 jiffies) to 1 second and removes the time that the transfer really takes out of the computation, as - per design - this is <30us and the jiffie resolution is 10ms so that does not make any difference what so ever. Signed-off-by: Martin Sperl <>
2015-05-18spi: bcm2835: enabling polling mode for transfers shorter than 30usMartin Sperl1-26/+86
In cases of short transfer times the CPU is spending lots of time in the interrupt handler and scheduler to reschedule the worker thread. Measurements show that we have times where it takes 29.32us to between the last clock change and the time that the worker-thread is running again returning from wait_for_completion_timeout(). During this time the interrupt-handler is running calling complete() and then also the scheduler is rescheduling the worker thread. This time can vary depending on how much of the code is still in CPU-caches, when there is a burst of spi transfers the subsequent delays are in the order of 25us, so the value of 30us seems reasonable. With polling the whole transfer of 4 bytes at 10MHz finishes after 6.16us (CS down to up) with the real transfer (clock running) taking 3.56us. So the efficiency has much improved and is also freeing CPU cycles, reducing interrupts and context switches. Because of the above 30us seems to be a reasonable limit for polling. Signed-off-by: Martin Sperl <> Signed-off-by: Mark Brown <>
2015-05-18spi: bcm2835: transform native-cs to gpio-cs on first spi_setupMartin Sperl1-5/+44
Transforms the bcm-2835 native SPI-chip select to their gpio-cs equivalent. This allows for some support of some optimizations that are not possible due to HW-gliches on the CS line - especially filling the FIFO before enabling SPI interrupts (by writing to CS register) while the transfer is already in progress (See commit: e3a2be3030e2) This patch also works arround some issues in bcm2835-pinctrl which does not set the value when setting the GPIO as output - it just sets up output and (typically) leaves the GPIO as low. When a fix for this is merged then this gpio_set_value can get removed from bcm2835_spi_setup. Signed-off-by: Martin Sperl <> Signed-off-by: Mark Brown <>
2015-05-18spi: bcm2835: fill FIFO before enabling interrupts to reduce interrupts/messageMartin Sperl1-0/+16
To reduce the number of interrupts/message we fill the FIFO before enabling interrupts - for short messages this reduces the interrupt count from 2 to 1 interrupt. There have been rare cases where short (<200ns) chip-select switches with native CS have been observed during such operation, this is why this optimization is only enabled for GPIO-CS. Signed-off-by: Martin Sperl <> Tested-by: Martin Sperl <> Signed-off-by: Mark Brown <>
2015-05-18spi: bcm2835: fix code formatting issueMartin Sperl1-2/+1
Signed-off-by: Martin Sperl <> Tested-by: Martin Sperl <> Signed-off-by: Mark Brown <>
2015-05-18spi: bcm2835: move to the transfer_one driver modelMartin Sperl1-88/+124
This also allows for GPIO-CS to get used removing the limitation of 2/3 SPI devises on the SPI bus. Fixes: spi-cs-high with native CS with multiple devices on the spi-bus resetting the chip selects to "normal" polarity after a finished transfer. No other functionality/improvements added. Tested with the following 4 devices on the spi-bus: * mcp2515 with native CS * mcp2515 with gpio CS * fb_st7735r with native CS (plus spi-cs-high via transistor inverting polarity) * enc28j60 with gpio-CS Tested-by: Martin Sperl <> Signed-off-by: Martin Sperl <> Signed-off-by: Mark Brown <>
2015-05-18spi: bcm2835: enable support of 3-wire modeMartin Sperl1-1/+5
Signed-off-by: Martin Sperl <> Signed-off-by: Mark Brown <>
2015-05-18spi: bcm2835: clock divider can be a multiple of 2Martin Sperl1-2/+3
The official documentation is wrong in this respect. Has been tested empirically for dividers 2-1024 Signed-off-by: Martin Sperl <> Signed-off-by: Mark Brown <>
2015-05-18spi: bcm2835: fill/drain SPI-fifo as much as possible during interruptMartin Sperl1-61/+17
Implement the recommendation from the BCM2835 data-sheet with regards to polling drivers to fill/drain the FIFO as much data as possible also for the interrupt-driven case (which this driver is making use of). This means that for long transfers (>64bytes) we need one interrupt every 64 bytes instead of every 12 bytes, as the FIFO is 16 words (not bytes) wide. Tested with mcp251x (can bus), fb_st7735 (TFT framebuffer device) and enc28j60 (ethernet) drivers. Signed-off-by: Martin Sperl <> Signed-off-by: Mark Brown <>
2015-05-18spi: bcm2835: fix all checkpath --strict messagesMartin Sperl1-7/+11
The following errors/warnings issued by --strict have been fixed: drivers/spi/spi-bcm2835.c:182: CHECK: Alignment should match open parenthesis drivers/spi/spi-bcm2835.c:191: CHECK: braces {} should be used on all arms of this statement drivers/spi/spi-bcm2835.c:234: CHECK: Alignment should match open parenthesis drivers/spi/spi-bcm2835.c:256: CHECK: Alignment should match open parenthesis drivers/spi/spi-bcm2835.c:271: CHECK: Alignment should match open parenthesis drivers/spi/spi-bcm2835.c:346: CHECK: Alignment should match open parenthesis total: 0 errors, 0 warnings, 6 checks, 403 lines checked In 2 locations the arguments had to get split/moved to the next line so that the line width stays below 80 chars. Signed-off-by: Martin Sperl <> Signed-off-by: Mark Brown <>
2015-05-18enc28j60: Add device tree compatible string and an overlayPhil Elwell1-0/+11
2015-05-18serial/amba-pl011: Refactor and simplify TX FIFO handlingDave Martin1-93/+26
Commit 734745c serial/amba-pl011: Activate TX IRQ passively adds some complexity and overhead in the form of a softirq mechanism for transmitting in the absence of interrupts. This patch simplifies the code flow to reduce the reliance on subtle behaviour and avoid fragility under future maintenance. To this end, the TX softirq mechanism is removed and instead pl011_start_tx() will now simply stuff the FIFO until full (guaranteeing future TX IRQs), or until there are no more chars to write (in which case we don't care whether an IRQ happens). Signed-off-by: Dave Martin <Dave.Martin@xxxxxxx> Signed-off-by: Jakub Kicinski <kubakici@xxxxx>
2015-05-18serial/amba-pl011: Activate TX IRQ passivelyDave Martin1-50/+115
The current PL011 driver transmits a dummy character when the UART is opened, to assert the TX IRQ for the first time (see pl011_startup()). The UART is put in loopback mode temporarily, so the receiver presumably shouldn't see anything. However... At least some platforms containing a PL011 send characters down the wire even when loopback mode is enabled. This means that a spurious NUL character may be seen at the receiver when the PL011 is opened through the TTY layer. The current code also temporarily sets the baud rate to maximum and the character width to the minimum, to that the dummy TX completes as quickly as possible. If this is seen by the receiver it will result in a framing error and can knock the receiver out of sync -- turning subsequent output into garbage until synchronisation is reestablished. (Particularly problematic during boot with systemd.) To avoid spurious transmissions, this patch removes assumptions about whether the TX IRQ will fire until at least one TX IRQ has been seen. Instead, the UART will unmask the TX IRQ and then slow-start via polling and timer-based soft IRQs initially. If the TTY layer writes enough data to fill the FIFO to the interrupt threshold in one go, the TX IRQ should assert, at which point the driver changes to fully interrupt-driven TX. In this way, the TX IRQ is activated as a side-effect instead of being done deliberately. This should also mean that the driver works on the SBSA Generic UART[1] (a cut-down PL011) without invasive changes. The Generic UART lacks some features needed for the dummy TX approach to work (FIFO disabling and loopback). [1] Server Base System Architecture (ARM-DEN-0029-v2.3) (click-thru required :/) Signed-off-by: Dave Martin <Dave.Martin@xxxxxxx>
2015-05-18pinctrl-bcm2835: Only request the interrupts listed in the DTBPhil Elwell1-0/+2
Although the GPIO controller can generate three interrupts (four counting the common one), the device tree files currently only specify two. In the absence of the third, simply don't register that interrupt (as opposed to registering 0), which has the effect of making it impossible to generate interrupts for GPIOs 46-53 which, since they share pins with the SD card interface, is unlikely to be a problem.
2015-05-18pinctrl-bcm2835: Fix interrupt handling for GPIOs 28-31 and 46-53Phil Elwell1-12/+39
Contrary to the documentation, the BCM2835 GPIO controller actually has four interrupt lines - one each for the three IRQ groups and one common. Rather confusingly, the GPIO interrupt groups don't correspond directly with the GPIO control banks. Instead, GPIOs 0-27 generate IRQ GPIO0, 28-45 GPIO1 and 46-53 GPIO2. Awkwardly, the GPIOS for IRQ GPIO1 straddle two 32-entry GPIO banks, so it is cleaner to split out a function to process the interrupts for a single GPIO bank. This bug has only just been observed because GPIOs above 27 can only be accessed on an old Raspberry Pi with the optional P5 header fitted, where the pins are often used for I2S instead.
2015-05-18Fix LED "input" trigger implementation for 3.19Phil Elwell2-16/+13
2015-05-18Fix grabbing lock from atomic context in i2c driverjeanleflambeur1-25/+65
2 main changes: - check for timeouts in the bcm2708_bsc_setup function as indicated by this comment: /* poll for transfer start bit (should only take 1-20 polls) */ This implies that the setup function can now fail so account for this everywhere it's called - Removed the clk_get_rate call from inside the setup function as it locks a mutex and that's not ok since we call it from under a spin lock. removed dead code and update comment fixed typo in comment
2015-05-18i2c_bcm2708: Fix clock reference countingPhil Elwell1-2/+10
2015-05-18w1-gpio: Sort out the pullup/parasitic power tanglePhil Elwell1-12/+24
2015-05-18pinctrl-bcm2835: bcm2835_gpio_direction_output must set the valuePhil Elwell1-1/+8
2015-05-18BCM270x_DT: Add pwr_led, and the required "input" triggerPhil Elwell3-0/+73
The "input" trigger makes the associated GPIO an input. This is to support the Raspberry Pi PWR LED, which is driven by external hardware in normal use. N.B. pwr_led is not available on Model A or B boards.
2015-05-18Update ds1307 driver for device-tree supportRyan Coe1-0/+8
Signed-off-by: Ryan Coe <>