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| author | Christophe Lyon <christophe.lyon@st.com> | 2011-02-09 13:19:15 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2011-02-09 19:47:20 +0100 |
| commit | acdf01effa1851780a731ca5ffeab79a474a6335 (patch) | |
| tree | 325d946ad1a0b8a04374e49ceaf48c4f53bb0665 | |
| parent | efd410373a4551911f3928bb2ccdf28792b294bf (diff) | |
| download | qemu-acdf01effa1851780a731ca5ffeab79a474a6335.tar.gz | |
target-arm: fix VSHLL Neon instruction.
Fix bit mask used when widening the result of shift on narrow input.
Signed-off-by: Christophe Lyon <christophe.lyon@st.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-arm/translate.c | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 89c916d3bc..ef3f36919d 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4880,16 +4880,28 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) /* The shift is less than the width of the source type, so we can just shift the whole register. */ tcg_gen_shli_i64(cpu_V0, cpu_V0, shift); + /* Widen the result of shift: we need to clear + * the potential overflow bits resulting from + * left bits of the narrow input appearing as + * right bits of left the neighbour narrow + * input. */ if (size < 2 || !u) { uint64_t imm64; if (size == 0) { imm = (0xffu >> (8 - shift)); imm |= imm << 16; - } else { + } else if (size == 1) { imm = 0xffff >> (16 - shift); + } else { + /* size == 2 */ + imm = 0xffffffff >> (32 - shift); + } + if (size < 2) { + imm64 = imm | (((uint64_t)imm) << 32); + } else { + imm64 = imm; } - imm64 = imm | (((uint64_t)imm) << 32); - tcg_gen_andi_i64(cpu_V0, cpu_V0, imm64); + tcg_gen_andi_i64(cpu_V0, cpu_V0, ~imm64); } } neon_store_reg64(cpu_V0, rd + pass); |