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| author | Stefan Weil <sw@weilnetz.de> | 2013-09-12 21:13:13 +0200 |
|---|---|---|
| committer | Stefan Weil <sw@weilnetz.de> | 2013-09-25 21:23:05 +0200 |
| commit | 3df2b8fde949be86d8a78923c992fdd698d4ea4c (patch) | |
| tree | 09c4db80712626acaed595506233559a2d4ebd2d | |
| parent | 6aa25b4a7bb10c48c3054f268d5be98e42ea42c0 (diff) | |
| download | qemu-3df2b8fde949be86d8a78923c992fdd698d4ea4c.tar.gz | |
misc: Use new rotate functions
Signed-off-by: Stefan Weil <sw@weilnetz.de>
| -rw-r--r-- | target-arm/iwmmxt_helper.c | 2 | ||||
| -rw-r--r-- | tcg/optimize.c | 12 | ||||
| -rw-r--r-- | tci.c | 8 |
3 files changed, 9 insertions, 13 deletions
diff --git a/target-arm/iwmmxt_helper.c b/target-arm/iwmmxt_helper.c index 7953b53f7e..e6cfa62da8 100644 --- a/target-arm/iwmmxt_helper.c +++ b/target-arm/iwmmxt_helper.c @@ -577,7 +577,7 @@ uint64_t HELPER(iwmmxt_rorl)(CPUARMState *env, uint64_t x, uint32_t n) uint64_t HELPER(iwmmxt_rorq)(CPUARMState *env, uint64_t x, uint32_t n) { - x = (x >> n) | (x << (64 - n)); + x = ror64(x, n); env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x); return x; } diff --git a/tcg/optimize.c b/tcg/optimize.c index b29bf25b67..89e2d6a3b3 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -238,20 +238,16 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg x, TCGArg y) return (int64_t)x >> (int64_t)y; case INDEX_op_rotr_i32: - x = ((uint32_t)x << (32 - y)) | ((uint32_t)x >> y); - return x; + return ror32(x, y); case INDEX_op_rotr_i64: - x = ((uint64_t)x << (64 - y)) | ((uint64_t)x >> y); - return x; + return ror64(x, y); case INDEX_op_rotl_i32: - x = ((uint32_t)x << y) | ((uint32_t)x >> (32 - y)); - return x; + return rol32(x, y); case INDEX_op_rotl_i64: - x = ((uint64_t)x << y) | ((uint64_t)x >> (64 - y)); - return x; + return rol64(x, y); CASE_OP_32_64(not): return ~x; @@ -688,13 +688,13 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t0 = *tb_ptr++; t1 = tci_read_ri32(&tb_ptr); t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (t1 << t2) | (t1 >> (32 - t2))); + tci_write_reg32(t0, rol32(t1, t2)); break; case INDEX_op_rotr_i32: t0 = *tb_ptr++; t1 = tci_read_ri32(&tb_ptr); t2 = tci_read_ri32(&tb_ptr); - tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2))); + tci_write_reg32(t0, ror32(t1, t2)); break; #endif #if TCG_TARGET_HAS_deposit_i32 @@ -955,13 +955,13 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) t0 = *tb_ptr++; t1 = tci_read_ri64(&tb_ptr); t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, (t1 << t2) | (t1 >> (64 - t2))); + tci_write_reg64(t0, rol64(t1, t2)); break; case INDEX_op_rotr_i64: t0 = *tb_ptr++; t1 = tci_read_ri64(&tb_ptr); t2 = tci_read_ri64(&tb_ptr); - tci_write_reg64(t0, (t1 >> t2) | (t1 << (64 - t2))); + tci_write_reg64(t0, ror64(t1, t2)); break; #endif #if TCG_TARGET_HAS_deposit_i64 |