diff options
| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2012-12-05 16:53:42 +1000 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2012-12-05 09:20:36 +0100 |
| commit | d4d230da08918183929c7d6cb54824b391536904 (patch) | |
| tree | 20778c617d57e72f4988c12d7a7bc448108d8361 | |
| parent | 16c6c80ac3a772b42a87b77dfdf0fdac7c607b0e (diff) | |
| download | qemu-d4d230da08918183929c7d6cb54824b391536904.tar.gz | |
xilinx_axienet: Implement R_IS behaviour
The interrupt status register R_IS is the standard clear-on-write behaviour.
This was unimplemented and defaulting to updating the register to the written
value. Implemented clear-on-write.
Reported-by: Jason Wu <huanyu@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
| -rw-r--r-- | hw/xilinx_axienet.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c index baae02bd66..f2e3bf1274 100644 --- a/hw/xilinx_axienet.c +++ b/hw/xilinx_axienet.c @@ -591,6 +591,10 @@ static void enet_write(void *opaque, hwaddr addr, s->maddr[s->fmi & 3][addr & 1] = value; break; + case R_IS: + s->regs[addr] &= ~value; + break; + case 0x8000 ... 0x83ff: s->ext_mtable[addr - 0x8000] = value; break; |