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| author | Michael Clark <mjc@sifive.com> | 2018-03-17 21:15:40 -0700 |
|---|---|---|
| committer | Michael Clark <mjc@sifive.com> | 2018-05-06 10:39:38 +1200 |
| commit | 8d196c43d7e247edbda7be7b1597ea184f6b498e (patch) | |
| tree | 8d30f86a0a44527b82023d9b52f1b01553a3e420 | |
| parent | 89854803ce3efb16fbc94604e652f152f5102569 (diff) | |
| download | qemu-8d196c43d7e247edbda7be7b1597ea184f6b498e.tar.gz | |
RISC-V: Remove erroneous comment from translate.c
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
| -rw-r--r-- | target/riscv/translate.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 808eab7f50..c3a029afef 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -280,7 +280,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, tcg_gen_andi_tl(source2, source2, 0x1F); tcg_gen_sar_tl(source1, source1, source2); break; - /* fall through to SRA */ #endif case OPC_RISC_SRA: tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1); |