diff options
author | Blue Swirl <blauwirbel@gmail.com> | 2009-07-31 07:26:44 +0000 |
---|---|---|
committer | Anthony Liguori <aliguori@us.ibm.com> | 2009-08-27 21:23:36 -0500 |
commit | 477806703a43558108cd1efbfb59a67c1d24e074 (patch) | |
tree | 91f6f9776eb503747a5be57837f70bf317b1ed92 | |
parent | b9369a384b10c934daab9de64fbff80b3659d837 (diff) | |
download | qemu-477806703a43558108cd1efbfb59a67c1d24e074.tar.gz |
esp: fix interrupt register read
Read of interrupt register should clear it and also sequence step and status.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
-rw-r--r-- | hw/esp.c | 13 |
1 files changed, 9 insertions, 4 deletions
@@ -422,7 +422,7 @@ static void parent_esp_reset(void *opaque, int irq, int level) static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) { ESPState *s = opaque; - uint32_t saddr; + uint32_t saddr, old_val; saddr = addr >> s->it_shift; DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]); @@ -445,10 +445,15 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr) } break; case ESP_RINTR: - // Clear interrupt/error status bits - s->rregs[ESP_RSTAT] &= ~(STAT_GE | STAT_PE); + /* Clear sequence step, interrupt register and all status bits + except TC */ + old_val = s->rregs[ESP_RINTR]; + s->rregs[ESP_RINTR] = 0; + s->rregs[ESP_RSTAT] &= ~STAT_TC; + s->rregs[ESP_RSEQ] = SEQ_CD; esp_lower_irq(s); - break; + + return old_val; default: break; } |