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| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-23 18:31:00 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-02-23 18:31:00 +0100 |
| commit | 915080e6b136f518793dba4232cbf3ed31a907a8 (patch) | |
| tree | 8e8ad89173cd0e8f70c753e6387f268593ffe813 | |
| parent | 9f59ddcc4fb4cf4f96b2751d4170596c8df19280 (diff) | |
| download | qemu-915080e6b136f518793dba4232cbf3ed31a907a8.tar.gz | |
target-mips: fix ROTR and DROTR by zero
Backported from HEAD (cc3f20fee2c9bea3793bf873c531ae6baf68df3a)
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | target-mips/translate.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index bf983821ac..f811f50c7f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1451,6 +1451,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc, tcg_gen_rotri_i32(t1, t1, uimm); tcg_gen_ext_i32_tl(cpu_gpr[rt], t1); tcg_temp_free_i32(t1); + } else { + tcg_gen_ext32s_tl(cpu_gpr[rt], t0); } opn = "rotr"; } else { @@ -1489,6 +1491,8 @@ static void gen_shift_imm(CPUState *env, DisasContext *ctx, uint32_t opc, if (env->insn_flags & ISA_MIPS32R2) { if (uimm != 0) { tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm); + } else { + tcg_gen_mov_tl(cpu_gpr[rt], t0); } opn = "drotr"; } else { |