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| author | Michael S. Tsirkin <mst@redhat.com> | 2010-07-12 15:13:02 +0300 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2010-07-12 15:13:02 +0300 |
| commit | d67eb20f6a387a10475b945c9e91fe2a00cffd93 (patch) | |
| tree | d8e00f9838f491100818fb9304054e41d28afcd5 | |
| parent | eb0557dbd1c045b57f1fa1ed5c2d22fbfd667583 (diff) | |
| parent | 935fc175597b2f1588a8030e0b8df07973b1c1db (diff) | |
| download | qemu-d67eb20f6a387a10475b945c9e91fe2a00cffd93.tar.gz | |
Merge branch 'master' into pci
| -rw-r--r-- | target-sh4/translate.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d0d6c00297..deee939e12 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1511,7 +1511,7 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free(addr); } return; -#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ +#define LD(reg,ldnum,ldpnum,prechk) \ case ldnum: \ prechk \ tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ @@ -1520,7 +1520,8 @@ static void _decode_opc(DisasContext * ctx) prechk \ tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ - return; \ + return; +#define ST(reg,stnum,stpnum,prechk) \ case stnum: \ prechk \ tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ @@ -1535,10 +1536,15 @@ static void _decode_opc(DisasContext * ctx) tcg_temp_free(addr); \ } \ return; +#define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \ + LD(reg,ldnum,ldpnum,prechk) \ + ST(reg,stnum,stpnum,prechk) LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) + ST(sgr, 0x003a, 0x4032, CHECK_PRIVILEGED) + LD(sgr, 0x403a, 0x4036, CHECK_PRIVILEGED if (!(ctx->features & SH_FEATURE_SH4A)) break;) LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) |