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| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-24 18:21:08 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-24 18:21:08 +0000 |
| commit | ac2e8522857ccf0977a91faae185d533b3812216 (patch) | |
| tree | bdda8ac049887b29f6ce21e40ec488e22eb7e9e6 | |
| parent | d2c639d6dc334a7de7c5b64caa6fc231d80084c5 (diff) | |
| download | qemu-ac2e8522857ccf0977a91faae185d533b3812216.tar.gz | |
sh4: sh_pci. Register resouces both at A7 and P4.
Add resource registration both for P4 and A7.
This is needed because of #5935 SH4: Eliminate P4 to A7 mangling.
Additionally, {reg,iop,mem}base which is no longer used are removed.
Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6433 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | hw/sh_pci.c | 17 |
1 files changed, 7 insertions, 10 deletions
diff --git a/hw/sh_pci.c b/hw/sh_pci.c index 5524c59897..9f89f2d94c 100644 --- a/hw/sh_pci.c +++ b/hw/sh_pci.c @@ -29,9 +29,6 @@ typedef struct { PCIBus *bus; PCIDevice *dev; - uint32_t regbase; - uint32_t iopbase; - uint32_t membase; uint32_t par; uint32_t mbr; uint32_t iobr; @@ -181,15 +178,15 @@ PCIBus *sh_pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, p->dev = pci_register_device(p->bus, "SH PCIC", sizeof(PCIDevice), -1, NULL, NULL); - p->regbase = 0x1e200000; - p->iopbase = 0x1e240000; - p->membase = 0xfd000000; reg = cpu_register_io_memory(0, sh_pci_reg.r, sh_pci_reg.w, p); - mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p); iop = cpu_register_io_memory(0, sh_pci_iop.r, sh_pci_iop.w, p); - cpu_register_physical_memory(p->regbase, 0x224, reg); - cpu_register_physical_memory(p->iopbase, 0x40000, iop); - cpu_register_physical_memory(p->membase, 0x1000000, mem); + mem = cpu_register_io_memory(0, sh_pci_mem.r, sh_pci_mem.w, p); + cpu_register_physical_memory(0x1e200000, 0x224, reg); + cpu_register_physical_memory(0x1e240000, 0x40000, iop); + cpu_register_physical_memory(0x1d000000, 0x1000000, mem); + cpu_register_physical_memory(0xfe200000, 0x224, reg); + cpu_register_physical_memory(0xfe240000, 0x40000, iop); + cpu_register_physical_memory(0xfd000000, 0x1000000, mem); p->dev->config[0x00] = 0x54; // HITACHI p->dev->config[0x01] = 0x10; // |