diff options
| author | Scott Wood <scottwood@freescale.com> | 2011-08-18 10:38:40 +0000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2011-10-06 09:48:04 +0200 |
| commit | 2bd9543cd303d9f6cbd37b7466bb03543035156b (patch) | |
| tree | 614611a0841a7a22949fdafe4a35bdbb407b320b | |
| parent | bebabbc7aa7d1c5a45ee325838adf58a19f1b1ee (diff) | |
| download | qemu-2bd9543cd303d9f6cbd37b7466bb03543035156b.tar.gz | |
ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pages
This definition is backward compatible with MAV=1.0 as long as
the guest does not set reserved bits in MAS1/MAS4.
Also, fix the shift in booke206_tlb_to_page_size -- it's the base
that should be able to hold a 4G page size, not the shift count.
Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | hw/ppce500_mpc8544ds.c | 2 | ||||
| -rw-r--r-- | target-ppc/cpu.h | 4 | ||||
| -rw-r--r-- | target-ppc/helper.c | 5 |
3 files changed, 6 insertions, 5 deletions
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index 61151d886c..8095516f43 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -174,7 +174,7 @@ out: /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */ static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size) { - return (ffs(size >> 10) - 1) >> 1; + return ffs(size >> 10) - 1; } static void mmubooke_create_initial_mapping(CPUState *env, diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 5200e6e8c6..32706dff7a 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -667,8 +667,8 @@ enum { #define MAS0_ATSEL_TLB 0 #define MAS0_ATSEL_LRAT MAS0_ATSEL -#define MAS1_TSIZE_SHIFT 8 -#define MAS1_TSIZE_MASK (0xf << MAS1_TSIZE_SHIFT) +#define MAS1_TSIZE_SHIFT 7 +#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT) #define MAS1_TS_SHIFT 12 #define MAS1_TS (1 << MAS1_TS_SHIFT) diff --git a/target-ppc/helper.c b/target-ppc/helper.c index 4b3731e88a..6339be3a75 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -1293,7 +1293,7 @@ target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb) { uint32_t tlbncfg; int tlbn = booke206_tlbm_to_tlbn(env, tlb); - target_phys_addr_t tlbm_size; + int tlbm_size; tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; @@ -1301,9 +1301,10 @@ target_phys_addr_t booke206_tlb_to_page_size(CPUState *env, ppcmas_tlb_t *tlb) tlbm_size = (tlb->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT; } else { tlbm_size = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; + tlbm_size <<= 1; } - return (1 << (tlbm_size << 1)) << 10; + return 1024ULL << tlbm_size; } /* TLB check function for MAS based SoftTLBs */ |