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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-19 19:14:10 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-11-19 19:14:10 +0000 |
| commit | d07b4d0ea72311b619c0f3799d849957446b5761 (patch) | |
| tree | 34318931cf7522d955675e67e07ac8542143e3d4 | |
| parent | 8d162c2b68db72623a507069fda0e35ccd1c6b85 (diff) | |
| download | qemu-d07b4d0ea72311b619c0f3799d849957446b5761.tar.gz | |
Fix MXCC register 64 bit read word order (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3709 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-sparc/op_helper.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 699a305b29..d22b2e8d37 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -196,8 +196,8 @@ void helper_ld_asi(int asi, int size, int sign) switch (T0) { case 0x01c00a00: /* MXCC control register */ if (size == 8) { - ret = env->mxccregs[3]; - T0 = env->mxccregs[3] >> 32; + ret = env->mxccregs[3] >> 32; + T0 = env->mxccregs[3]; } else DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); break; @@ -217,8 +217,8 @@ void helper_ld_asi(int asi, int size, int sign) break; case 0x01c00f00: /* MBus port address register */ if (size == 8) { - ret = env->mxccregs[7]; - T0 = env->mxccregs[7] >> 32; + ret = env->mxccregs[7] >> 32; + T0 = env->mxccregs[7]; } else DPRINTF_MXCC("%08x: unimplemented access size: %d\n", T0, size); break; |