diff options
| author | Paolo Bonzini <pbonzini@redhat.com> | 2014-04-29 13:10:05 +0200 |
|---|---|---|
| committer | Michael Roth <mdroth@linux.vnet.ibm.com> | 2014-07-20 22:13:08 -0500 |
| commit | 46a1b0e489cdb604da81ebde985c35ff798601dc (patch) | |
| tree | 0505a6111c0741e92bcd4e2782ad593a82dbabb4 | |
| parent | a14d42919f5108c92fd576ddd7bf2b3759593a98 (diff) | |
| download | qemu-46a1b0e489cdb604da81ebde985c35ff798601dc.tar.gz | |
target-i386: fix set of registers zeroed on reset
BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they
should be (Intel Instruction Set Extensions Programming Reference
319433-015, pages 9-4 and 9-6). Same for YMM.
XCR0 should be reset to 1.
TSC and TSC_RESET were zeroed already by the memset, remove the explicit
assignments.
Cc: Andreas Faerber <afaerber@suse.de>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
(cherry picked from commit 05e7e819d7d159a75a46354aead95e1199b8f168)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
| -rw-r--r-- | target-i386/cpu.c | 3 | ||||
| -rw-r--r-- | target-i386/cpu.h | 11 |
2 files changed, 7 insertions, 7 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 8fd1497dc4..553d0b8d29 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2476,8 +2476,7 @@ static void x86_cpu_reset(CPUState *s) cpu_breakpoint_remove_all(s, BP_CPU); cpu_watchpoint_remove_all(s, BP_CPU); - env->tsc_adjust = 0; - env->tsc = 0; + env->xcr0 = 1; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2a22a7d64e..e2244e9d7d 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -797,6 +797,10 @@ typedef struct CPUX86State { target_ulong cr[5]; /* NOTE: cr1 is unused */ int32_t a20_mask; + BNDReg bnd_regs[4]; + BNDCSReg bndcs_regs; + uint64_t msr_bndcfgs; + /* FPU state */ unsigned int fpstt; /* top of stack index */ uint16_t fpus; @@ -819,6 +823,8 @@ typedef struct CPUX86State { XMMReg xmm_t0; MMXReg mmx_t0; + XMMReg ymmh_regs[CPU_NB_REGS]; + /* sysenter registers */ uint32_t sysenter_cs; target_ulong sysenter_esp; @@ -928,12 +934,7 @@ typedef struct CPUX86State { uint16_t fpus_vmstate; uint16_t fptag_vmstate; uint16_t fpregs_format_vmstate; - uint64_t xstate_bv; - XMMReg ymmh_regs[CPU_NB_REGS]; - BNDReg bnd_regs[4]; - BNDCSReg bndcs_regs; - uint64_t msr_bndcfgs; uint64_t xcr0; |