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authorPeter Maydell <peter.maydell@linaro.org>2014-08-29 15:00:28 +0100
committerMichael Roth <mdroth@linux.vnet.ibm.com>2014-09-10 09:30:57 -0500
commit4fd144f8f52cdc99c0bdcfc2021219f483d997f8 (patch)
tree8b0ea0a3f7ff91fb57526d59595366bf73feaf17
parentea774b8dd05cf3fb66af191343e25e33f9a8aa13 (diff)
downloadqemu-4fd144f8f52cdc99c0bdcfc2021219f483d997f8.tar.gz
target-arm: Correct Cortex-A57 ISAR5 and AA64ISAR0 ID register values
We implement the crypto extensions but were incorrectly reporting ID register values for the Cortex-A57 which did not advertise crypto. Use the correct values as described in the TRM. With this fix Linux correctly detects presence of the crypto features and advertises them in /proc/cpuinfo. Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1408718660-7295-1-git-send-email-peter.maydell@linaro.org Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> (cherry picked from commit c379621451e64cad166a60f42e1d67f0438b8d1b) Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
-rw-r--r--target-arm/cpu64.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 8b2081c246..b2ed01f667 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -123,9 +123,10 @@ static void aarch64_a57_initfn(Object *obj)
cpu->id_isar2 = 0x21232042;
cpu->id_isar3 = 0x01112131;
cpu->id_isar4 = 0x00011142;
+ cpu->id_isar5 = 0x00011121;
cpu->id_aa64pfr0 = 0x00002222;
cpu->id_aa64dfr0 = 0x10305106;
- cpu->id_aa64isar0 = 0x00010000;
+ cpu->id_aa64isar0 = 0x00011120;
cpu->id_aa64mmfr0 = 0x00001124;
cpu->clidr = 0x0a200023;
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */