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authorAlistair Francis <alistair.francis@xilinx.com>2017-08-15 07:57:12 -0700
committerPeter Maydell <peter.maydell@linaro.org>2017-08-15 16:11:22 +0100
commit955fd0ad5d610f62ba2f4ce46a872bf50434dcf8 (patch)
treeb5d0584c14452bec0c6a2be2d02f06a07f4b792f
parent47025a0193f1f910300adfa443305ccf8482ef87 (diff)
downloadqemu-955fd0ad5d610f62ba2f4ce46a872bf50434dcf8.tar.gz
target/arm: Correct exclusive store cmpxchg memop mask
When we perform the atomic_cmpxchg operation we want to perform the operation on a pair of 32-bit registers. Previously we were just passing the register size in which was set to MO_32. This would result in the high register to be ignored. To fix this issue we hardcode the size to be 64-bits long when operating on 32-bit pairs. Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Portia Stephens <portia.stephens@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20170815145714.17635-2-richard.henderson@linaro.org Message-Id: <bc18dddca56e8c2ea4a3def48d33ceb5d21d1fff.1502488636.git.alistair.francis@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/translate-a64.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 58ed4c6d05..113e2e172b 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1913,7 +1913,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
tcg_gen_concat32_i64(val, cpu_exclusive_val, cpu_exclusive_high);
tcg_gen_atomic_cmpxchg_i64(tmp, addr, val, tmp,
get_mem_index(s),
- size | MO_ALIGN | s->be_data);
+ MO_64 | MO_ALIGN | s->be_data);
tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, val);
tcg_temp_free_i64(val);
} else if (s->be_data == MO_LE) {