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authorKuo-Jung Su <dantesu@gmail.com>2013-03-05 21:27:24 +0000
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2013-03-07 09:27:11 +0100
commit0bc472a9d6b80567c212023c5eae413f4dfb53ad (patch)
tree804d7b2326c560f28b6c4f4a84e10c376643d4e3
parent76c48503c4c87afabf0c93acf78480f65276844d (diff)
downloadqemu-0bc472a9d6b80567c212023c5eae413f4dfb53ad.tar.gz
hw/nand.c: correct the sense of the BUSY/READY status bit
The BIT6 of Status Register(SR): SR[6] behaves the same as R/B# pin SR[6] = 0 indicates the device is busy; SR[6] = 1 means the device is ready Some NAND flash controller (i.e. ftnandc021) relies on the SR[6] to determine if the NAND flash erase/program is success or error timeout. P.S: The exmaple NAND flash datasheet could be found at following link: http://www.mxic.com.tw/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Index/8FEA549237D2F7674825795800104C26/$File/MX30LF1G08AA,%203V,%201Gb,%20v1.1.pdf Signed-off-by: Kuo-Jung Su <dantesu@gmail.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
-rw-r--r--hw/nand.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/nand.c b/hw/nand.c
index 4a71265ed3..61e918fa83 100644
--- a/hw/nand.c
+++ b/hw/nand.c
@@ -46,7 +46,7 @@
# define NAND_IOSTATUS_PLANE1 (1 << 2)
# define NAND_IOSTATUS_PLANE2 (1 << 3)
# define NAND_IOSTATUS_PLANE3 (1 << 4)
-# define NAND_IOSTATUS_BUSY (1 << 6)
+# define NAND_IOSTATUS_READY (1 << 6)
# define NAND_IOSTATUS_UNPROTCT (1 << 7)
# define MAX_PAGE 0x800
@@ -231,6 +231,7 @@ static void nand_reset(DeviceState *dev)
s->iolen = 0;
s->offset = 0;
s->status &= NAND_IOSTATUS_UNPROTCT;
+ s->status |= NAND_IOSTATUS_READY;
}
static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)