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authorBlue Swirl <blauwirbel@gmail.com>2012-12-08 17:50:57 +0000
committerBlue Swirl <blauwirbel@gmail.com>2012-12-08 17:50:57 +0000
commit536b558f5896ebbd635b57fa393e82faaa32ad52 (patch)
tree61756309c1d8f338f943f69bfbe6e6e50128da92
parent511c68d3af626cb0a39034cb77e7ac64d3a26c0c (diff)
parent19e6c50d2d843220efbdd3b2db21d83c122c364a (diff)
downloadqemu-536b558f5896ebbd635b57fa393e82faaa32ad52.tar.gz
Merge branch 'master' of git.qemu-project.org:/pub/git/qemu
* 'master' of git.qemu-project.org:/pub/git/qemu: target-mips: Fix incorrect shift for SHILO and SHILOV target-mips: Fix incorrect code and test for INSV xilinx_uartlite: Accept input after rx FIFO pop xilinx_uartlite: suppress "cannot receive message" xilinx_axienet: Implement R_IS behaviour
-rw-r--r--hw/xilinx_axienet.c4
-rw-r--r--hw/xilinx_uartlite.c7
-rw-r--r--target-mips/dsp_helper.c19
-rw-r--r--tests/tcg/mips/mips32-dsp/insv.c2
-rw-r--r--tests/tcg/mips/mips32-dsp/shilo.c18
-rw-r--r--tests/tcg/mips/mips32-dsp/shilov.c20
6 files changed, 55 insertions, 15 deletions
diff --git a/hw/xilinx_axienet.c b/hw/xilinx_axienet.c
index baae02bd66..f2e3bf1274 100644
--- a/hw/xilinx_axienet.c
+++ b/hw/xilinx_axienet.c
@@ -591,6 +591,10 @@ static void enet_write(void *opaque, hwaddr addr,
s->maddr[s->fmi & 3][addr & 1] = value;
break;
+ case R_IS:
+ s->regs[addr] &= ~value;
+ break;
+
case 0x8000 ... 0x83ff:
s->ext_mtable[addr - 0x8000] = value;
break;
diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c
index d20fc4124b..02c5850331 100644
--- a/hw/xilinx_uartlite.c
+++ b/hw/xilinx_uartlite.c
@@ -97,6 +97,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
s->rx_fifo_len--;
uart_update_status(s);
uart_update_irq(s);
+ qemu_chr_accept_input(s->chr);
break;
default:
@@ -182,12 +183,8 @@ static void uart_rx(void *opaque, const uint8_t *buf, int size)
static int uart_can_rx(void *opaque)
{
struct xlx_uartlite *s = opaque;
- int r;
- r = s->rx_fifo_len < sizeof(s->rx_fifo);
- if (!r)
- printf("cannot receive!\n");
- return r;
+ return s->rx_fifo_len < sizeof(s->rx_fifo);
}
static void uart_event(void *opaque, int event)
diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c
index e7949c22c0..14daf91950 100644
--- a/target-mips/dsp_helper.c
+++ b/target-mips/dsp_helper.c
@@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
\
filter = ((int32_t)0x01 << size) - 1; \
filter = filter << pos; \
- temprs = rs & filter; \
+ temprs = (rs << pos) & filter; \
temprt = rt & ~filter; \
temp = temprs | temprt; \
\
@@ -3814,17 +3814,18 @@ void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env)
rs5_0 = rs & 0x3F;
rs5_0 = (int8_t)(rs5_0 << 2) >> 2;
- rs5_0 = MIPSDSP_ABS(rs5_0);
+
+ if (unlikely(rs5_0 == 0)) {
+ return;
+ }
+
acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) |
((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO);
- if (rs5_0 == 0) {
- temp = acc;
+
+ if (rs5_0 > 0) {
+ temp = acc >> rs5_0;
} else {
- if (rs5_0 > 0) {
- temp = acc >> rs5_0;
- } else {
- temp = acc << rs5_0;
- }
+ temp = acc << -rs5_0;
}
env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32);
diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c
index 7e3b047606..243b00733d 100644
--- a/tests/tcg/mips/mips32-dsp/insv.c
+++ b/tests/tcg/mips/mips32-dsp/insv.c
@@ -10,7 +10,7 @@ int main()
dsp = 0x305;
rt = 0x12345678;
rs = 0x87654321;
- result = 0x12345338;
+ result = 0x12345438;
__asm
("wrdsp %2, 0x03\n\t"
"insv %0, %1\n\t"
diff --git a/tests/tcg/mips/mips32-dsp/shilo.c b/tests/tcg/mips/mips32-dsp/shilo.c
index b686616d80..ce8ebc69c2 100644
--- a/tests/tcg/mips/mips32-dsp/shilo.c
+++ b/tests/tcg/mips/mips32-dsp/shilo.c
@@ -23,5 +23,23 @@ int main()
assert(ach == resulth);
assert(acl == resultl);
+
+ ach = 0x1;
+ acl = 0x80000000;
+
+ resulth = 0x3;
+ resultl = 0x0;
+
+ __asm
+ ("mthi %0, $ac1\n\t"
+ "mtlo %1, $ac1\n\t"
+ "shilo $ac1, -1\n\t"
+ "mfhi %0, $ac1\n\t"
+ "mflo %1, $ac1\n\t"
+ : "+r"(ach), "+r"(acl)
+ );
+ assert(ach == resulth);
+ assert(acl == resultl);
+
return 0;
}
diff --git a/tests/tcg/mips/mips32-dsp/shilov.c b/tests/tcg/mips/mips32-dsp/shilov.c
index f186032a14..e1d6cea4b6 100644
--- a/tests/tcg/mips/mips32-dsp/shilov.c
+++ b/tests/tcg/mips/mips32-dsp/shilov.c
@@ -25,5 +25,25 @@ int main()
assert(ach == resulth);
assert(acl == resultl);
+
+ rs = 0xffffffff;
+ ach = 0x1;
+ acl = 0x80000000;
+
+ resulth = 0x3;
+ resultl = 0x0;
+
+ __asm
+ ("mthi %0, $ac1\n\t"
+ "mtlo %1, $ac1\n\t"
+ "shilov $ac1, %2\n\t"
+ "mfhi %0, $ac1\n\t"
+ "mflo %1, $ac1\n\t"
+ : "+r"(ach), "+r"(acl)
+ : "r"(rs)
+ );
+ assert(ach == resulth);
+ assert(acl == resultl);
+
return 0;
}