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| author | Leon Alrae <leon.alrae@imgtec.com> | 2016-07-28 09:28:23 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-07-28 11:24:02 +0100 |
| commit | 701074a6fc7470d0ed54e4a4bcd4d491ad8da22e (patch) | |
| tree | c26c573b4740af5dd41346aa58c254618717104c | |
| parent | 7f81dbb9a0e89b5306c1337e0cd0e1cea8a03f6d (diff) | |
| download | qemu-701074a6fc7470d0ed54e4a4bcd4d491ad8da22e.tar.gz | |
target-mips: fix EntryHi.EHINV being cleared on TLB exception
While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| -rw-r--r-- | target-mips/helper.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-mips/helper.c b/target-mips/helper.c index 9fbca26d41..c864b15b97 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -396,6 +396,7 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, env->CP0_Context = (env->CP0_Context & ~0x007fffff) | ((address >> 9) & 0x007ffff0); env->CP0_EntryHi = (env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask) | + (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) | (address & (TARGET_PAGE_MASK << 1)); #if defined(TARGET_MIPS64) env->CP0_EntryHi &= env->SEGMask; |