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authorKONRAD Frederic <frederic.konrad@adacore.com>2018-05-03 17:17:15 +0200
committerMichael Clark <mjc@sifive.com>2018-05-09 07:57:46 +1200
commit6fad7d1893f6ea926063067af957009bc320406f (patch)
treeb49b54fd58d26203dbc863cec652cf32bc381225
parent17b9751e85b9989cc841ed387794d7f1e8aa5e46 (diff)
downloadqemu-6fad7d1893f6ea926063067af957009bc320406f.tar.gz
riscv: htif: increase the priority of the htif subregion
The htif device is supposed to be mapped over an other subregion. So increase its priority to one to avoid any conflict. Here is the output of info mtree: Before: (qemu) info mtree address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart 0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom 0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint 0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram address-space: I/O 0000000000000000-000000000000ffff (prio 0, i/o): io address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000000f (prio 0, i/o): riscv.htif.uart 0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom 0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint 0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram After: (qemu) info mtree address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart 0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom 0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint 0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram address-space: I/O 0000000000000000-000000000000ffff (prio 0, i/o): io address-space: cpu-memory-0 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000000f (prio 1, i/o): riscv.htif.uart 0000000000000000-0000000000011fff (prio 0, ram): riscv.spike.bootrom 0000000002000000-000000000200ffff (prio 0, i/o): riscv.sifive.clint 0000000080000000-0000000087ffffff (prio 0, ram): riscv.spike.ram Reviewed-by: Michael Clark <mjc@sifive.com> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Signed-off-by: Michael Clark <mjc@sifive.com> Message-Id: <1525360636-18229-3-git-send-email-frederic.konrad@adacore.com>
-rw-r--r--hw/riscv/riscv_htif.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/riscv/riscv_htif.c b/hw/riscv/riscv_htif.c
index be252ec8cc..f73512941f 100644
--- a/hw/riscv/riscv_htif.c
+++ b/hw/riscv/riscv_htif.c
@@ -253,8 +253,9 @@ HTIFState *htif_mm_init(MemoryRegion *address_space, MemoryRegion *main_mem,
htif_be_change, s, NULL, true);
if (address_symbol_set == 3) {
memory_region_init_io(&s->mmio, NULL, &htif_mm_ops, s,
- TYPE_HTIF_UART, size);
- memory_region_add_subregion(address_space, base, &s->mmio);
+ TYPE_HTIF_UART, size);
+ memory_region_add_subregion_overlap(address_space, base,
+ &s->mmio, 1);
}
return s;