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authorAnthony Liguori <aliguori@us.ibm.com>2012-03-12 20:50:09 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2012-03-12 20:50:09 -0500
commit79122e933cd8bda0917c56c1bdac3f2b8d49fb23 (patch)
tree024464f125c49fd112a43df397ecedec8616a64e /cpu-all.h
parentcbedde09698d3506da429ae305dcea7f7deee554 (diff)
parent97161e177b4ea2730dff13c4df01475762ab6048 (diff)
downloadqemu-79122e933cd8bda0917c56c1bdac3f2b8d49fb23.tar.gz
Merge remote-tracking branch 'qemu-kvm/memory/core' into staging
* qemu-kvm/memory/core: memory: get rid of cpu_register_io_memory() memory: dispatch directly via MemoryRegion exec: fix code tlb entry misused as iotlb in get_page_addr_code() memory: store section indices in iotlb instead of io indices memory: make phys_page_find() return an unadjusted section
Diffstat (limited to 'cpu-all.h')
-rw-r--r--cpu-all.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/cpu-all.h b/cpu-all.h
index a174532b19..f7f6e7acd3 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -498,14 +498,6 @@ extern RAMList ram_list;
extern const char *mem_path;
extern int mem_prealloc;
-/* physical memory access */
-
-/* MMIO pages are identified by a combination of an IO device index and
- 3 flags. The ROMD code stores the page ram offset in iotlb entry,
- so only a limited number of ids are avaiable. */
-
-#define IO_MEM_NB_ENTRIES (1 << TARGET_PAGE_BITS)
-
/* Flags stored in the low bits of the TLB virtual address. These are
defined so that fast path ram access is all zeros. */
/* Zero if TLB entry is valid. */