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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-10-23 16:35:43 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-10-23 16:35:43 +0100 |
| commit | bc79082e4cd12c1241fa03b0abceacf45f537740 (patch) | |
| tree | f07a84ff8655bd6b7e57e50252edf6697d1101e2 /default-configs/pci.mak | |
| parent | 1e700f4c6cddaf29ce1d205f0f8e8b9255481930 (diff) | |
| parent | 31bfa2a40004204aee503c6417fbafb5d17e0a51 (diff) | |
| download | qemu-bc79082e4cd12c1241fa03b0abceacf45f537740.tar.gz | |
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging
X86 queue, 2015-10-23
# gpg: Signature made Fri 23 Oct 2015 16:30:58 BST using RSA key ID 984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
* remotes/ehabkost/tags/x86-pull-request:
vl: trivial: minor tweaks to a max-cpu error msg
target-i386: Use 1UL for bit shift
target-i386: Add DE to TCG_FEATURES
target-i386: Ensure always-1 bits on DR6 can't be cleared
target-i386: Check CR4[DE] for processing DR4/DR5
target-i386: Handle I/O breakpoints
target-i386: Optimize setting dr[0-3]
target-i386: Move hw_*breakpoint_* functions
target-i386: Ensure bit 10 on DR7 is never cleared
target-i386: Re-introduce optimal breakpoint removal
target-i386: Introduce cpu_x86_update_dr7
target-i386: Disable cache info passthrough by default
target-i386: allow any alignment for SMBASE
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'default-configs/pci.mak')
0 files changed, 0 insertions, 0 deletions