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authorAnthony Liguori <aliguori@us.ibm.com>2013-04-19 08:38:05 -0500
committerAnthony Liguori <aliguori@us.ibm.com>2013-04-19 08:38:05 -0500
commit5dff24bebae5103810002ea76b1d03927e2148f2 (patch)
treed5eb86de23120163ca1b2965b119e5e8c69c8bad /docs/specs/pci-testdev.txt
parentb6c99f8a6d66c5fa01a60483d9b012eb2b0932f2 (diff)
parent22773d6066a7f01a95f78c270edf9dbd2e755ac3 (diff)
downloadqemu-5dff24bebae5103810002ea76b1d03927e2148f2.tar.gz
Merge remote-tracking branch 'mst/tags/for_anthony' into staging
pci: add pci test device This adds a new device that we can use for testing PCI PIO and MMIO, with and without ioeventfd in different configurations. FAST_MMIO will be added if/when kvm supports it. Also included are minor cleanups in kvm APIs that it needs. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Mon 15 Apr 2013 05:42:24 PM CDT using RSA key ID D28D5469 # gpg: Can't check signature: public key not found # By Michael S. Tsirkin # Via Michael S. Tsirkin * mst/tags/for_anthony: pci: add pci test device kvm: support non datamatch ioeventfd kvm: support any size for pio eventfd kvm: remove unused APIs Message-id: cover.1366272004.git.mst@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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+pci-test is a device used for testing low level IO
+
+device implements up to two BARs: BAR0 and BAR1.
+Each BAR can be memory or IO. Guests must detect
+BAR type and act accordingly.
+
+Each BAR size is up to 4K bytes.
+Each BAR starts with the following header:
+
+typedef struct PCITestDevHdr {
+ uint8_t test; <- write-only, starts a given test number
+ uint8_t width_type; <- read-only, type and width of access for a given test.
+ 1,2,4 for byte,word or long write.
+ any other value if test not supported on this BAR
+ uint8_t pad0[2];
+ uint32_t offset; <- read-only, offset in this BAR for a given test
+ uint32_t data; <- read-only, data to use for a given test
+ uint32_t count; <- for debugging. number of writes detected.
+ uint8_t name[]; <- for debugging. 0-terminated ASCII string.
+} PCITestDevHdr;
+
+All registers are little endian.
+
+device is expected to always implement tests 0 to N on each BAR, and to add new
+tests with higher numbers. In this way a guest can scan test numbers until it
+detects an access type that it does not support on this BAR, then stop.