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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2013-02-28 18:23:13 +0000
committerPeter Maydell <peter.maydell@linaro.org>2013-02-28 18:23:13 +0000
commitcde4577f11cd557cfd48d752b7a0929d19eac9e9 (patch)
tree1fa3078af05c84f29e90f0c1cba8eefc2df14ea5 /hw/a9mpcore.c
parent845769fc6319d308a39a78734c6dc03fa93ff2c5 (diff)
downloadqemu-cde4577f11cd557cfd48d752b7a0929d19eac9e9.tar.gz
arm: mptimer: Remove WDT distinction
In QEMU emulation, there is no functional difference between the ARM mpcore private timers and watchdogs. Removed all the distinction between the two from arm_mptimer.c and converted it to be just the mptimer. a9mpcore and arm11mpcore just instantiate the same mptimer object twice to get both timer and WDT. If in the future we want to make the WDT functionally different then we can use either QOM hierarchy to derive WDT from from mptimer, or we can add a property "is-wdt" or some such. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/a9mpcore.c')
-rw-r--r--hw/a9mpcore.c18
1 files changed, 12 insertions, 6 deletions
diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
index 33b9e07f46..0032f53c04 100644
--- a/hw/a9mpcore.c
+++ b/hw/a9mpcore.c
@@ -21,6 +21,7 @@ typedef struct A9MPPrivState {
MemoryRegion scu_iomem;
MemoryRegion container;
DeviceState *mptimer;
+ DeviceState *wdt;
DeviceState *gic;
uint32_t num_irq;
} A9MPPrivState;
@@ -129,7 +130,7 @@ static void a9mp_priv_set_irq(void *opaque, int irq, int level)
static int a9mp_priv_init(SysBusDevice *dev)
{
A9MPPrivState *s = FROM_SYSBUS(A9MPPrivState, dev);
- SysBusDevice *busdev, *gicbusdev;
+ SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev;
int i;
s->gic = qdev_create(NULL, "arm_gic");
@@ -147,7 +148,12 @@ static int a9mp_priv_init(SysBusDevice *dev)
s->mptimer = qdev_create(NULL, "arm_mptimer");
qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu);
qdev_init_nofail(s->mptimer);
- busdev = SYS_BUS_DEVICE(s->mptimer);
+ timerbusdev = SYS_BUS_DEVICE(s->mptimer);
+
+ s->wdt = qdev_create(NULL, "arm_mptimer");
+ qdev_prop_set_uint32(s->wdt, "num-cpu", s->num_cpu);
+ qdev_init_nofail(s->wdt);
+ wdtbusdev = SYS_BUS_DEVICE(s->wdt);
/* Memory map (addresses are offsets from PERIPHBASE):
* 0x0000-0x00ff -- Snoop Control Unit
@@ -170,9 +176,9 @@ static int a9mp_priv_init(SysBusDevice *dev)
* memory region, not the "timer/watchdog for core X" ones 11MPcore has.
*/
memory_region_add_subregion(&s->container, 0x600,
- sysbus_mmio_get_region(busdev, 0));
+ sysbus_mmio_get_region(timerbusdev, 0));
memory_region_add_subregion(&s->container, 0x620,
- sysbus_mmio_get_region(busdev, 1));
+ sysbus_mmio_get_region(wdtbusdev, 0));
memory_region_add_subregion(&s->container, 0x1000,
sysbus_mmio_get_region(gicbusdev, 0));
@@ -183,9 +189,9 @@ static int a9mp_priv_init(SysBusDevice *dev)
*/
for (i = 0; i < s->num_cpu; i++) {
int ppibase = (s->num_irq - 32) + i * 32;
- sysbus_connect_irq(busdev, i * 2,
+ sysbus_connect_irq(timerbusdev, i,
qdev_get_gpio_in(s->gic, ppibase + 29));
- sysbus_connect_irq(busdev, i * 2 + 1,
+ sysbus_connect_irq(wdtbusdev, i,
qdev_get_gpio_in(s->gic, ppibase + 30));
}
return 0;