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| author | Andreas Färber <afaerber@suse.de> | 2012-12-17 06:18:02 +0100 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-01-15 04:09:13 +0100 |
| commit | 55e5c2850293547203874098f7cec148ffd12dfa (patch) | |
| tree | f9a9cc316999b7b52726b5186a925022b3747daa /hw/alpha_typhoon.c | |
| parent | 1b1ed8dc40635d60dd95c04658989af63542fcbf (diff) | |
| download | qemu-55e5c2850293547203874098f7cec148ffd12dfa.tar.gz | |
cpu: Move cpu_index field to CPUState
Note that target-alpha accesses this field from TCG, now using a
negative offset. Therefore the field is placed last in CPUState.
Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change.
Move common parts of mips cpu_state_reset() to mips_cpu_reset().
Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
[AF: Rebased onto ppc CPU subclasses and openpic changes]
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'hw/alpha_typhoon.c')
| -rw-r--r-- | hw/alpha_typhoon.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/hw/alpha_typhoon.c b/hw/alpha_typhoon.c index dafb35ddd1..bf9aabfc08 100644 --- a/hw/alpha_typhoon.c +++ b/hw/alpha_typhoon.c @@ -75,6 +75,7 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) { CPUAlphaState *env = cpu_single_env; TyphoonState *s = opaque; + CPUState *cpu; uint64_t ret = 0; if (addr & 4) { @@ -95,7 +96,8 @@ static uint64_t cchip_read(void *opaque, hwaddr addr, unsigned size) case 0x0080: /* MISC: Miscellaneous Register. */ - ret = s->cchip.misc | (env->cpu_index & 3); + cpu = ENV_GET_CPU(env); + ret = s->cchip.misc | (cpu->cpu_index & 3); break; case 0x00c0: |