diff options
| author | Cédric Le Goater <clg@kaod.org> | 2016-09-22 18:13:05 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-09-22 18:13:05 +0100 |
| commit | 8da33ef757d6d49b41432a22e4ab357652ec0e14 (patch) | |
| tree | 3924058ddd750d7bfccdd195730aaf9d25862f10 /hw/arm/aspeed.c | |
| parent | c3ba99f723af21f27d0f6c839443b218c75b0dc0 (diff) | |
| download | qemu-8da33ef757d6d49b41432a22e4ab357652ec0e14.tar.gz | |
hw/misc: use macros to define hw-strap1 register on the AST2400 Aspeed SoC
This gives some explanation behind the magic number 0x120CE416.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1473438177-26079-8-git-send-email-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/aspeed.c')
| -rw-r--r-- | hw/arm/aspeed.c | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index b4eb8049af..c08213c04e 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -40,8 +40,21 @@ enum { PALMETTO_BMC, }; +#define PALMETTO_BMC_HW_STRAP1 ( \ + SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ + SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \ + SCU_AST2400_HW_STRAP_ACPI_DIS | \ + SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \ + SCU_HW_STRAP_VGA_CLASS_CODE | \ + SCU_HW_STRAP_LPC_RESET_PIN | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \ + SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ + SCU_HW_STRAP_SPI_WIDTH | \ + SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ + SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) + static const AspeedBoardConfig aspeed_boards[] = { - [PALMETTO_BMC] = { "ast2400-a0", 0x120CE416 }, + [PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 }, }; static void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, |