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authorPeter Maydell <peter.maydell@linaro.org>2014-11-03 16:43:32 +0000
committerPeter Maydell <peter.maydell@linaro.org>2014-11-03 16:43:32 +0000
commiteb5f222b5c125de1b47970c6096a3107ffe1d69b (patch)
tree1a52e60e8070f9b664f761bce085edde569a5986 /hw/arm/boot.c
parent7135781f65f1267a72bf554ee2b7bd605f9e59aa (diff)
parent437a8c11c06f53ed3bcdcc3e5abc5d20b2d439bd (diff)
downloadqemu-eb5f222b5c125de1b47970c6096a3107ffe1d69b.tar.gz
Merge remote-tracking branch 'remotes/xtensa/tags/20141103-xtensa' into staging
Xtensa fixes and improvements 2014-11-03: - build fixes for cores w/o windowed registers and with profiling interrupts; - fix uImage load address for MMUv2 cores; - add script for automatic core import from xtensa configuration overlay. # gpg: Signature made Sun 02 Nov 2014 22:04:44 GMT using RSA key ID F83FA044 # gpg: Good signature from "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" * remotes/xtensa/tags/20141103-xtensa: MAINTAINERS: update xtensa boards target-xtensa: fix build for cores w/o windowed registers target-xtensa: add core importing script hw/xtensa/xtfpga: treat uImage load address as virtual hw/core/loader: implement address translation in uimage loader target-xtensa: avoid duplicate timer interrupt delivery target-xtensa: tests: pre-process tests linker script target-xtensa: add definition for XTHAL_INTTYPE_PROFILING Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/boot.c')
-rw-r--r--hw/arm/boot.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index bffbea5e0e..0014c34ddd 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -580,7 +580,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
entry = elf_entry;
if (kernel_size < 0) {
kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
- &is_linux);
+ &is_linux, NULL, NULL);
}
/* On aarch64, it's the bootloader's job to uncompress the kernel. */
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) && kernel_size < 0) {