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authorPeter Maydell <peter.maydell@linaro.org>2013-04-19 11:15:20 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-04-19 11:15:20 +0100
commit7468d73ac9a514b33c0c2797a1238db11163b23b (patch)
tree9aec449d3c8a1c241caafc76e841b8b5df262546 /hw/arm/versatilepb.c
parent66a96d7018b9cbabb73c9b87b62a37e4cc46580a (diff)
downloadqemu-7468d73ac9a514b33c0c2797a1238db11163b23b.tar.gz
versatile_pci: Implement the PCI controller's control registers
The versatile_pci PCI controller has a set of control registers which handle the mapping between PCI and system address spaces. Implement these registers (though for now they have no effect since we don't implement mapping PCI space into system memory at all). The most natural order for our sysbus regions has the control registers at the start, so move all the others down one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Paul Brook <paul@codesourcery.com>
Diffstat (limited to 'hw/arm/versatilepb.c')
-rw-r--r--hw/arm/versatilepb.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 33a8222845..8128fcdf10 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -224,9 +224,10 @@ static void versatile_init(QEMUMachineInitArgs *args, int board_id)
dev = qdev_create(NULL, "versatile_pci");
busdev = SYS_BUS_DEVICE(dev);
qdev_init_nofail(dev);
- sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
- sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
- sysbus_mmio_map(busdev, 2, 0x43000000); /* PCI I/O */
+ sysbus_mmio_map(busdev, 0, 0x10001000); /* PCI controller regs */
+ sysbus_mmio_map(busdev, 1, 0x41000000); /* PCI self-config */
+ sysbus_mmio_map(busdev, 2, 0x42000000); /* PCI config */
+ sysbus_mmio_map(busdev, 3, 0x43000000); /* PCI I/O */
sysbus_connect_irq(busdev, 0, sic[27]);
sysbus_connect_irq(busdev, 1, sic[28]);
sysbus_connect_irq(busdev, 2, sic[29]);