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authorPeter Maydell <peter.maydell@linaro.org>2012-05-02 16:49:39 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-06-19 13:24:44 +0000
commitc48c6522f550b9b704f7324164b00b5770ec7345 (patch)
treea5f501720f44e20f94ee985ce9c46b0154ed9445 /hw/armv7m_nvic.c
parentacd684280f9e91e8199d0b2126d4b057676dafec (diff)
downloadqemu-c48c6522f550b9b704f7324164b00b5770ec7345.tar.gz
hw/arm_gic: Remove the special casing of NCPU for the NVIC
Drop the special casing of NCPU=1 for the NVIC. This slightly increases the amount of memory used by its state structure, but removes some ifdeffery and means we can safely move the GIC state into a common subclass structure. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/armv7m_nvic.c')
-rw-r--r--hw/armv7m_nvic.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 986a6bbd0c..99a87a28bf 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -389,9 +389,8 @@ static int armv7m_nvic_init(SysBusDevice *dev)
{
nvic_state *s= FROM_SYSBUSGIC(nvic_state, dev);
- /* note that for the M profile gic_init() takes the number of external
- * interrupt lines only.
- */
+ /* The NVIC always has only one CPU */
+ s->gic.num_cpu = 1;
gic_init(&s->gic, s->num_irq);
memory_region_add_subregion(get_system_memory(), 0xe000e000, &s->gic.iomem);
s->systick.timer = qemu_new_timer_ns(vm_clock, systick_timer_tick, s);