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| author | Roy Franz <roy.franz@linaro.org> | 2013-12-17 19:42:27 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-12-17 19:42:27 +0000 |
| commit | fa21a7b13e97120c789eda1dbae87a9bcb1efe09 (patch) | |
| tree | 87e8d2840f4c42cb72d9c1b04b0d3271b0547c2a /hw/block | |
| parent | b8433303fbc5a4a694adb0f0aff5059442ae63e3 (diff) | |
| download | qemu-fa21a7b13e97120c789eda1dbae87a9bcb1efe09.tar.gz | |
Add max device width parameter for NOR devices
For handling CFI and device ID reads, we need to not only know the
width that a NOR flash device is configured for, but also its maximum
width. The maximum width addressing mode is used for multi-width
parts no matter which width they are configured for. The most common
case is x16 parts that also support x8 mode. When configured for x8
operation these devices respond to CFI and device ID requests differently
than native x8 NOR parts.
Signed-off-by: Roy Franz <roy.franz@linaro.org>
Message-id: 1386279359-32286-6-git-send-email-roy.franz@linaro.org
[PMM: Added comment explaining the semantics of width vs device-width
vs max-device-width]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/block')
| -rw-r--r-- | hw/block/pflash_cfi01.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 82a2519113..de7a6c0847 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -74,6 +74,7 @@ struct pflash_t { uint64_t sector_len; uint8_t bank_width; uint8_t device_width; /* If 0, device width not specified. */ + uint8_t max_device_width; /* max device width in bytes */ uint8_t be; uint8_t wcycle; /* if 0, the flash is read normally */ int ro; @@ -635,6 +636,13 @@ static void pflash_cfi01_realize(DeviceState *dev, Error **errp) pfl->ro = 0; } + /* Default to devices being used at their maximum device width. This was + * assumed before the device_width support was added. + */ + if (!pfl->max_device_width) { + pfl->max_device_width = pfl->device_width; + } + pfl->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, pflash_timer, pfl); pfl->wcycle = 0; pfl->cmd = 0; @@ -728,8 +736,25 @@ static Property pflash_cfi01_properties[] = { DEFINE_PROP_DRIVE("drive", struct pflash_t, bs), DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0), + /* width here is the overall width of this QEMU device in bytes. + * The QEMU device may be emulating a number of flash devices + * wired up in parallel; the width of each individual flash + * device should be specified via device-width. If the individual + * devices have a maximum width which is greater than the width + * they are being used for, this maximum width should be set via + * max-device-width (which otherwise defaults to device-width). + * So for instance a 32-bit wide QEMU flash device made from four + * 16-bit flash devices used in 8-bit wide mode would be configured + * with width = 4, device-width = 1, max-device-width = 2. + * + * If device-width is not specified we default to backwards + * compatible behaviour which is a bad emulation of two + * 16 bit devices making up a 32 bit wide QEMU device. This + * is deprecated for new uses of this device. + */ DEFINE_PROP_UINT8("width", struct pflash_t, bank_width, 0), DEFINE_PROP_UINT8("device-width", struct pflash_t, device_width, 0), + DEFINE_PROP_UINT8("max-device-width", struct pflash_t, max_device_width, 0), DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), |