diff options
| author | Maksim Kozlov <m.kozlov@samsung.com> | 2012-02-16 09:56:05 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-02-17 11:13:07 +0000 |
| commit | df91b48f64075595e25a269befed5e4fe75501cb (patch) | |
| tree | 4097fa5a7eb1c4dded82df81194729f7110f303e /hw/exynos4210.c | |
| parent | 62db8bf39b8a0e3edb631a3d0e5bde840c780fcf (diff) | |
| download | qemu-df91b48f64075595e25a269befed5e4fe75501cb.tar.gz | |
ARM: exynos4210: basic Power Management Unit implementation
Patch adds basic model for Exynos4210 SoC PMU.
This model implements PMU registers just as a bulk of memory. Currently,
the only reason this device exists is that secondary CPU boot loader
uses PMU INFORM5 register as a holding pen.
Signed-off-by: Maksim Kozlov <m.kozlov@samsung.com>
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/exynos4210.c')
| -rw-r--r-- | hw/exynos4210.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/hw/exynos4210.c b/hw/exynos4210.c index 8ebe5df407..f922f5572b 100644 --- a/hw/exynos4210.c +++ b/hw/exynos4210.c @@ -52,6 +52,9 @@ #define EXYNOS4210_EXT_COMBINER_BASE_ADDR 0x10440000 #define EXYNOS4210_INT_COMBINER_BASE_ADDR 0x10448000 +/* PMU SFR base address */ +#define EXYNOS4210_PMU_BASE_ADDR 0x10020000 + static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; @@ -202,6 +205,12 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, &s->dram0_mem); + /* PMU. + * The only reason of existence at the moment is that secondary CPU boot + * loader uses PMU INFORM5 register as a holding pen. + */ + sysbus_create_simple("exynos4210.pmu", EXYNOS4210_PMU_BASE_ADDR, NULL); + /* PWM */ sysbus_create_varargs("exynos4210.pwm", EXYNOS4210_PWM_BASE_ADDR, s->irq_table[exynos4210_get_irq(22, 0)], |