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author | Anthony Liguori <aliguori@us.ibm.com> | 2011-12-14 07:59:21 -0600 |
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committer | Anthony Liguori <aliguori@us.ibm.com> | 2011-12-14 07:59:21 -0600 |
commit | 9423a2e8dd362a271bfe194ec131062814557b95 (patch) | |
tree | 6b10b2d69e5d81b6ff4cb2ba75693d8a65362d92 /hw/gusemu_hal.c | |
parent | da5361cc685c004d8bb4e7c5e7b3a52c7aca2c56 (diff) | |
parent | 126c79133f77d1b0b7c3849899c6d5f83b2fd410 (diff) | |
download | qemu-9423a2e8dd362a271bfe194ec131062814557b95.tar.gz |
Merge remote-tracking branch 'stefanha/trivial-patches-next' into staging
Diffstat (limited to 'hw/gusemu_hal.c')
-rw-r--r-- | hw/gusemu_hal.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/gusemu_hal.c b/hw/gusemu_hal.c index c6f9537483..6096690735 100644 --- a/hw/gusemu_hal.c +++ b/hw/gusemu_hal.c @@ -502,7 +502,7 @@ void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int coun /* this function gets called by the callback function as soon as a DMA transfer is about to start * dma_addr is a translated address within accessible memory, not the physical one, * count is (real dma count register)+1 - * note that the amount of bytes transfered is fully determined by values in the DMA registers + * note that the amount of bytes transferred is fully determined by values in the DMA registers * do not forget to update DMA states after transferring the entire block: * DREQ cleared & TC asserted after the _whole_ transfer */ @@ -517,7 +517,7 @@ void gus_dma_transferdata(GUSEmuState * state, char *dma_addr, unsigned int coun int offset = (GUSregw(GUS42DMAStart) << 4) + (GUSregb(GUS50DMAHigh) & 0xf); if (state->gusdma >= 4) offset = (offset & 0xc0000) + (2 * (offset & 0x1fff0)); /* 16 bit address translation */ - destaddr = (char *) state->himemaddr + offset; /* wavetable RAM adress */ + destaddr = (char *) state->himemaddr + offset; /* wavetable RAM address */ } GUSregw(GUS42DMAStart) += (GUSword) (count >> 4); /* ToDo: add 16bit GUS page limit? */ |