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| author | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:47 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-06-17 15:23:51 +0100 |
| commit | c84428b33fc2d88f17c3f599a9e5d17ae23422c1 (patch) | |
| tree | 7b90ac41e1d64014bbf87d6afd7065f6ccd03560 /hw/intc/arm_gicv3.c | |
| parent | 287c181ae4132d7cc75ea422051f2c90e90b6493 (diff) | |
| download | qemu-c84428b33fc2d88f17c3f599a9e5d17ae23422c1.tar.gz | |
hw/intc/arm_gicv3: Implement gicv3_set_irq()
Implement the code which updates the GIC state when an interrupt
input into the GIC is asserted.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-15-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'hw/intc/arm_gicv3.c')
| -rw-r--r-- | hw/intc/arm_gicv3.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 4c1fbb6850..65ebca2e0a 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -311,7 +311,25 @@ static void gicv3_set_irq(void *opaque, int irq, int level) * [N+32..N+63] : PPI (internal interrupts for CPU 1 * ... */ - /* Do nothing for now */ + GICv3State *s = opaque; + + if (irq < (s->num_irq - GIC_INTERNAL)) { + /* external interrupt (SPI) */ + gicv3_dist_set_irq(s, irq + GIC_INTERNAL, level); + } else { + /* per-cpu interrupt (PPI) */ + int cpu; + + irq -= (s->num_irq - GIC_INTERNAL); + cpu = irq / GIC_INTERNAL; + irq %= GIC_INTERNAL; + assert(cpu < s->num_cpu); + /* Raising SGIs via this function would be a bug in how the board + * model wires up interrupts. + */ + assert(irq >= GIC_NR_SGIS); + gicv3_redist_set_irq(&s->cpu[cpu], irq, level); + } } static void arm_gicv3_post_load(GICv3State *s) |