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| author | Andreas Färber <afaerber@suse.de> | 2013-01-17 22:30:20 +0100 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-03-12 10:35:55 +0100 |
| commit | d8ed887bdcd29ce2e967f8b15a6a2b6dcaa11cd5 (patch) | |
| tree | 57f8deccddd53e7aab5ca75d1d194da635a35790 /hw/mips | |
| parent | 259186a7d2f7184efc96ae99bc5658e6159f53ad (diff) | |
| download | qemu-d8ed887bdcd29ce2e967f8b15a6a2b6dcaa11cd5.tar.gz | |
exec: Pass CPUState to cpu_reset_interrupt()
Move it to qom/cpu.c to avoid build failures depending on include order
of cpu-qom.h and exec/cpu-all.h.
Change opaques of various ..._irq_handler() functions to the
appropriate CPU type to facilitate using cpu_reset_interrupt().
Fix Coding Style issues while at it (missing braces, indentation).
Signed-off-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'hw/mips')
| -rw-r--r-- | hw/mips/mips_int.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index ddd3b1bb01..3a78999e02 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -26,7 +26,9 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) { - CPUMIPSState *env = (CPUMIPSState *)opaque; + MIPSCPU *cpu = opaque; + CPUMIPSState *env = &cpu->env; + CPUState *cs = CPU(cpu); if (irq < 0 || irq > 7) return; @@ -40,7 +42,7 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level) if (env->CP0_Cause & CP0Ca_IP_mask) { cpu_interrupt(env, CPU_INTERRUPT_HARD); } else { - cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } } @@ -49,7 +51,7 @@ void cpu_mips_irq_init_cpu(CPUMIPSState *env) qemu_irq *qi; int i; - qi = qemu_allocate_irqs(cpu_mips_irq_request, env, 8); + qi = qemu_allocate_irqs(cpu_mips_irq_request, mips_env_get_cpu(env), 8); for (i = 0; i < 8; i++) { env->irq[i] = qi[i]; } |