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| author | Miodrag Dinic <miodrag.dinic@imgtec.com> | 2015-12-03 16:48:57 +0100 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2016-01-23 14:30:04 +0000 |
| commit | 51243852af322f0a1103a90c936c43db84def82f (patch) | |
| tree | c48b75c9bd394803217186b933c258f10f30c955 /hw/mips | |
| parent | 1aa56f6ee7d2375b0734e98ba69cc41416894bbc (diff) | |
| download | qemu-51243852af322f0a1103a90c936c43db84def82f.tar.gz | |
target-mips: Fix ALIGN instruction when bp=0
If executing ALIGN with shift count bp=0 within mips64 emulation,
the result of the operation should be sign extended.
Taken from the official documentation (pseudo code) :
ALIGN:
tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp)
tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp))
tmp = tmp_rt_hi || tmp_rt_lo
GPR[rd] = sign_extend.32(tmp)
Signed-off-by: Miodrag Dinic <miodrag.dinic@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Diffstat (limited to 'hw/mips')
0 files changed, 0 insertions, 0 deletions