diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-18 12:43:40 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-03-18 12:43:40 +0000 |
| commit | 39d51eb8bcc603c02342d8f5e1f7a569e5f17e06 (patch) | |
| tree | 3036073718e3ba76bc3143261d6caee489d03538 /hw/mips_int.c | |
| parent | 36f696517b1723d627b79aa924bac7c678de01b0 (diff) | |
| download | qemu-39d51eb8bcc603c02342d8f5e1f7a569e5f17e06.tar.gz | |
Fix BD flag handling, cause register contents, implement some more bits
for R2 interrupt handling.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2493 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/mips_int.c')
| -rw-r--r-- | hw/mips_int.c | 13 |
1 files changed, 4 insertions, 9 deletions
diff --git a/hw/mips_int.c b/hw/mips_int.c index 93d599fc60..7f9f15305b 100644 --- a/hw/mips_int.c +++ b/hw/mips_int.c @@ -20,20 +20,15 @@ void cpu_mips_update_irq(CPUState *env) void cpu_mips_irq_request(void *opaque, int irq, int level) { - CPUState *env = first_cpu; - - uint32_t mask; + CPUState *env = (CPUState *)opaque; - if (irq >= 16) + if (irq < 0 || irq > 7) return; - mask = 1 << (irq + CP0Ca_IP); - if (level) { - env->CP0_Cause |= mask; + env->CP0_Cause |= 1 << (irq + CP0Ca_IP); } else { - env->CP0_Cause &= ~mask; + env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP)); } cpu_mips_update_irq(env); } - |