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| author | Jan Kiszka <jan.kiszka@siemens.com> | 2009-05-02 00:29:37 +0200 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2009-05-22 10:50:34 -0500 |
| commit | 8217606e6edb49591b4a6fd5a0d1229cebe470a9 (patch) | |
| tree | fff3d6f590833c0f894a6c7c300ab126b5259d95 /hw/mips_malta.c | |
| parent | 93102fd6010c68320bc9a008c8cf70cb4a36d4b9 (diff) | |
| download | qemu-8217606e6edb49591b4a6fd5a0d1229cebe470a9.tar.gz | |
Introduce reset notifier order
Add the parameter 'order' to qemu_register_reset and sort callbacks on
registration. On system reset, callbacks with lower order will be
invoked before those with higher order. Update all existing users to the
standard order 0.
Note: At least for x86, the existing users seem to assume that handlers
are called in their registration order. Therefore, the patch preserves
this property. If someone feels bored, (s)he could try to identify this
dependency and express it properly on callback registration.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/mips_malta.c')
| -rw-r--r-- | hw/mips_malta.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/mips_malta.c b/hw/mips_malta.c index d8621824cb..e71ecc124e 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -447,7 +447,7 @@ static MaltaFPGAState *malta_fpga_init(target_phys_addr_t base, qemu_irq uart_ir s->uart = serial_mm_init(base + 0x900, 3, uart_irq, 230400, uart_chr, 1); malta_fpga_reset(s); - qemu_register_reset(malta_fpga_reset, s); + qemu_register_reset(malta_fpga_reset, 0, s); return s; } @@ -792,7 +792,7 @@ void mips_malta_init (ram_addr_t ram_size, fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - qemu_register_reset(main_cpu_reset, env); + qemu_register_reset(main_cpu_reset, 0, env); /* allocate RAM */ if (ram_size > (256 << 20)) { |