target-mips: CP0 Random register improvements

- Use a LFSR to generate the random value
- Make sure to not return the same value twice

Based on a patch by Hervé Poussineau.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6233 c046a42c-6fe2-441c-8c8c-71466251a162

1 files changed, 8 insertions, 3 deletions

diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index 13217b2da0..67b873511c 100644
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -7,10 +7,15 @@
 /* XXX: do not use a global */
 uint32_t cpu_mips_get_random (CPUState *env)
 {
-    static uint32_t seed = 0;
+    static uint32_t lfsr = 1;
+    static uint32_t prev_idx = 0;
     uint32_t idx;
-    seed = seed * 314159 + 1;
-    idx = (seed >> 16) % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+    /* Don't return same value twice, so get another value */
+    do {
+        lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
+        idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+    } while (idx == prev_idx);
+    prev_idx = idx;
     return idx;
 }