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| author | Alexander Graf <agraf@suse.de> | 2014-07-13 16:55:53 +0200 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-09-08 12:50:51 +0200 |
| commit | b19eae18c1cdf053fd85a39902cf77d8b561ef76 (patch) | |
| tree | a74692c935ee2fba876d72ba33bd9d3f5d2e0bd8 /hw/nvram | |
| parent | a8b0503701ed8de9353834b0955260f4d9f08640 (diff) | |
| download | qemu-b19eae18c1cdf053fd85a39902cf77d8b561ef76.tar.gz | |
PPC: mac_nvram: Allow 2 and 4 byte accesses
The NVRAM in our Core99 machine really supports 2byte and 4byte accesses
just as well as 1byte accesses. In fact, Mac OS X uses those.
Add support for higher register size granularities.
Signed-off-by: Alexander Graf <agraf@suse.de>
Diffstat (limited to 'hw/nvram')
| -rw-r--r-- | hw/nvram/mac_nvram.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/nvram/mac_nvram.c b/hw/nvram/mac_nvram.c index bcff074d81..7656951e99 100644 --- a/hw/nvram/mac_nvram.c +++ b/hw/nvram/mac_nvram.c @@ -66,6 +66,10 @@ static uint64_t macio_nvram_readb(void *opaque, hwaddr addr, static const MemoryRegionOps macio_nvram_ops = { .read = macio_nvram_readb, .write = macio_nvram_writeb, + .valid.min_access_size = 1, + .valid.max_access_size = 4, + .impl.min_access_size = 1, + .impl.max_access_size = 1, .endianness = DEVICE_BIG_ENDIAN, }; |