diff options
| author | Richard Henderson <rth@twiddle.net> | 2017-02-08 15:06:54 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-02-14 08:14:58 +1100 |
| commit | 4a09d0bb34ab030e09e87173b2e3ec0fd7616cff (patch) | |
| tree | 4ed7ec1405016274a6e6ad540a4135101c27e570 /hw/openrisc | |
| parent | 305e6c8a2ff7a6e3f4942b50e853230f18eeb5a9 (diff) | |
| download | qemu-4a09d0bb34ab030e09e87173b2e3ec0fd7616cff.tar.gz | |
target/openrisc: Rename the cpu from or32 to or1k
This is in keeping with the toolchain and or1ksim.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'hw/openrisc')
| -rw-r--r-- | hw/openrisc/openrisc_sim.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 6d06d5be01..fc0d0967b7 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -139,10 +139,10 @@ static void openrisc_sim_init(MachineState *machine) static void openrisc_sim_machine_init(MachineClass *mc) { - mc->desc = "or32 simulation"; + mc->desc = "or1k simulation"; mc->init = openrisc_sim_init; mc->max_cpus = 1; mc->is_default = 1; } -DEFINE_MACHINE("or32-sim", openrisc_sim_machine_init) +DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init) |