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authorPeter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>2012-06-13 14:46:43 +1000
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2012-06-15 13:08:13 +0200
commitabe098e4f93a80b0756c0e8e728bc78c47a91127 (patch)
tree3f2145d259d793c7a9b8678b854c304acd8356a6 /hw/petalogix_s3adsp1800_mmu.c
parent8d4eb373f7e32305af2a0e04bbc24fa3494ffe6f (diff)
downloadqemu-abe098e4f93a80b0756c0e8e728bc78c47a91127.tar.gz
xilinx_timer: changed nr_timers to one_timer_only
The configurable property for this IP in the Xilinx tools is a boolean switch "one-timer-only" that flicks this timer from being dual channel to single. Updated QEMU to work the same way for better match with the IP core and its TRM. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Diffstat (limited to 'hw/petalogix_s3adsp1800_mmu.c')
-rw-r--r--hw/petalogix_s3adsp1800_mmu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c
index 7d83c21036..2cf68828ed 100644
--- a/hw/petalogix_s3adsp1800_mmu.c
+++ b/hw/petalogix_s3adsp1800_mmu.c
@@ -106,7 +106,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR, irq[3]);
/* 2 timers at irq 2 @ 62 Mhz. */
- xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000);
+ xilinx_timer_create(TIMER_BASEADDR, irq[0], 0, 62 * 1000000);
xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);
microblaze_load_kernel(cpu, ddr_base, ram_size,