diff options
| author | Avi Kivity <avi@redhat.com> | 2011-08-15 17:17:27 +0300 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2011-08-22 10:47:42 -0500 |
| commit | b6dcbe086c77ec683f5ff0b693593cda1d61f3a1 (patch) | |
| tree | 4db9e86c6c9f303d4496af5d98533cf051000650 /hw/ppc405_uc.c | |
| parent | 9074e0e3e8b087fcc14b0ae76fb240ae9872e70c (diff) | |
| download | qemu-b6dcbe086c77ec683f5ff0b693593cda1d61f3a1.tar.gz | |
ppc4xx_sdram: convert to memory API
Clumsy due to the lack of clipping support, needed for
changing exposed ram size.
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/ppc405_uc.c')
| -rw-r--r-- | hw/ppc405_uc.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 03b25928f6..9d5d2af5d8 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -2107,7 +2107,8 @@ static void ppc405cr_cpc_init (CPUState *env, clk_setup_t clk_setup[7], qemu_register_reset(ppc405cr_cpc_reset, cpc); } -CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], +CPUState *ppc405cr_init (MemoryRegion ram_memories[4], + target_phys_addr_t ram_bases[4], target_phys_addr_t ram_sizes[4], uint32_t sysclk, qemu_irq **picp, int do_init) @@ -2136,7 +2137,8 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); *picp = pic; /* SDRAM controller */ - ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[14], 1, ram_memories, + ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ @@ -2451,7 +2453,8 @@ static void ppc405ep_cpc_init (CPUState *env, clk_setup_t clk_setup[8], #endif } -CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], +CPUState *ppc405ep_init (MemoryRegion ram_memories[2], + target_phys_addr_t ram_bases[2], target_phys_addr_t ram_sizes[2], uint32_t sysclk, qemu_irq **picp, int do_init) @@ -2485,7 +2488,8 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], *picp = pic; /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[17], 2, ram_memories, + ram_bases, ram_sizes, do_init); /* External bus controller */ ppc405_ebc_init(env); /* DMA controller */ |