diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-15 22:59:45 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-15 22:59:45 +0000 |
| commit | 80e8bd2b0fe8afe3d5f2bd4960ab83514d97b992 (patch) | |
| tree | 5e93124b9cffc36505e0bdae87ff9b1a40f5abdf /hw/ppc405_uc.c | |
| parent | 61b244050334f88de5bed0c8cd8af8503aaa0931 (diff) | |
| download | qemu-80e8bd2b0fe8afe3d5f2bd4960ab83514d97b992.tar.gz | |
target-ppc: rename ppc405_sdram_init() to ppc4xx_sdram_init()
The SDRAM controller is shared across almost all 405 and 440 embedded
processors, with some slight differences such as the sizes supported for each
memory bank.
Rename only; no functional changes.
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6062 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/ppc405_uc.c')
| -rw-r--r-- | hw/ppc405_uc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c index 7e7fb38e7a..9275416a15 100644 --- a/hw/ppc405_uc.c +++ b/hw/ppc405_uc.c @@ -2230,7 +2230,7 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4], pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); *picp = pic; /* SDRAM controller */ - ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init); offset = 0; for (i = 0; i < 4; i++) offset += ram_sizes[i]; @@ -2588,7 +2588,7 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2], *picp = pic; /* SDRAM controller */ /* XXX 405EP has no ECC interrupt */ - ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); + ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init); offset = 0; for (i = 0; i < 2; i++) offset += ram_sizes[i]; |